AxiMonAxiL Entity Reference

Inheritance diagram for AxiMonAxiL:

Collaboration diagram for AxiMonAxiL:

Entities
AxiMonAxiL.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
AXI_CLK_FREQ_G	real := 156 . 25E + 6
AXI_NUM_SLOTS_G	positive := 1
AXI_CONFIG_G	AxiConfigType

Ports
axiClk	in	sl
axiRst	in	sl
axiWriteMasters	in	AxiWriteMasterArray ( AXI_NUM_SLOTS_G- 1 downto 0 )
axiWriteSlaves	in	AxiWriteSlaveArray ( AXI_NUM_SLOTS_G- 1 downto 0 )
axiReadMasters	in	AxiReadMasterArray ( AXI_NUM_SLOTS_G- 1 downto 0 )
axiReadSlaves	in	AxiReadSlaveArray ( AXI_NUM_SLOTS_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiMonAxiL.vhd
• build/SRC_VHDL/surf/AxiMonAxiL.vhd