Architecture >> AxiMonAxiL::mapping
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AXIS_CONFIG_C | AxiStreamConfigType := ( TSTRB_EN_C = > AXI_STREAM_CONFIG_INIT_C.TSTRB_EN_C , TDATA_BYTES_C = > AXI_CONFIG_G.DATA_BYTES_C , TDEST_BITS_C = > AXI_STREAM_CONFIG_INIT_C.TDEST_BITS_C , TID_BITS_C = > AXI_STREAM_CONFIG_INIT_C.TID_BITS_C , TKEEP_MODE_C = > AXI_STREAM_CONFIG_INIT_C.TKEEP_MODE_C , TUSER_BITS_C = > AXI_STREAM_CONFIG_INIT_C.TUSER_BITS_C , TUSER_MODE_C = > AXI_STREAM_CONFIG_INIT_C.TUSER_MODE_C ) |
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axisMasters | AxiStreamMasterArray ( 2 * AXI_NUM_SLOTS_G- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C ) |
axisSlaves | AxiStreamSlaveArray ( 2 * AXI_NUM_SLOTS_G- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C ) |
The documentation for this design unit was generated from the following files:
- axi/axi4/rtl/AxiMonAxiL.vhd
- build/SRC_VHDL/surf/AxiMonAxiL.vhd