AxiLiteWriteFilterTb.tb Architecture Reference

Architecture >> AxiLiteWriteFilterTb::tb

Processes
test
test

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := ( CLK_PERIOD_C/ 4 )

Signals
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
filterWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
filterWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axilClk	sl := ' 0 '
axilRst	sl := ' 1 '
enFilter	sl := ' 1 '
blockAll	sl := ' 1 '

Instantiations
u_axilclk	ClkRst <Entity ClkRst>
u_filter	AxiLiteWriteFilter <Entity AxiLiteWriteFilter>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_axilclk	ClkRst <Entity ClkRst>
u_filter	AxiLiteWriteFilter <Entity AxiLiteWriteFilter>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd
• build/SRC_VHDL/surf/AxiLiteWriteFilterTb.vhd