AxiLiteWriteFilter Entity Reference

Inheritance diagram for AxiLiteWriteFilter:

Entities
AxiLiteWriteFilter.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
FILTER_SIZE_G	positive := 1
FILTER_ADDR_G	Slv32Array := ( 0 = > x " 00000000 " )

Ports
axilClk	in	sl
axilRst	in	sl
enFilter	in	sl := ' 1 '
blockAll	in	sl := ' 1 '
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteWriteFilter.vhd
• build/SRC_VHDL/surf/AxiLiteWriteFilter.vhd