AxiLiteWriteFilter.rtl Architecture Reference

Architecture >> AxiLiteWriteFilter::rtl

Processes
comb	( axilRst , blockAll , enFilter , mAxilWriteSlave , r , sAxilWriteMaster )
seq	( axilClk , axilRst )
comb	( axilRst , blockAll , enFilter , mAxilWriteSlave , r , sAxilWriteMaster )
seq	( axilClk , axilRst )

Constants
REG_INIT_C	RegType := ( validAddress = > ' 1 ' , idx = > 0 , sAxilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , mAxilWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , LOOP_ARRAY_S , CHECK_FLAG_S , MOVE_S , BUS_RESP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteWriteFilter.vhd
• build/SRC_VHDL/surf/AxiLiteWriteFilter.vhd