AxiLiteWriteFilterIpIntegrator.rtl Architecture Reference

Architecture >> AxiLiteWriteFilterIpIntegrator::rtl

Constants
FILTER_ADDR_C	Slv32Array ( FILTER_SIZE_G- 1 downto 0 ) := ( 0 = > toSlv ( FILTER_ADDR_0_G , 32 ) , others = > toSlv ( FILTER_ADDR_0_G , 32 ) )

Signals
sAxiAResetN	sl := ' 1 '
mAxiAResetN	sl := ' 1 '
sAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
sAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
sAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
sAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
mAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
mAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
mAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
mAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_slaveshim	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_mastershim	MasterAxiLiteIpIntegrator <Entity MasterAxiLiteIpIntegrator>
u_dut	AxiLiteWriteFilter <Entity AxiLiteWriteFilter>

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd