Architecture >> AxiLiteSrpV0Wrapper::rtl

Constants
TPD_C	time := 10 ns/ 4
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 16 )

Signals
axisRst	sl := ' 0 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayeraxil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiLiteSrpV0 <Entity AxiLiteSrpV0>

The documentation for this design unit was generated from the following file:

Constants

Signals