Architecture >> AxiLiteSrpV0Tb::tb

Constants
TPD_G	time := 1 ns
RESP_THOLD_G	integer range 0 to ( 2 24 ) := 1**
SLAVE_READY_EN_G	boolean := true
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 9
FIFO_PAUSE_THRESH_G	integer range 1 to ( 2 24 ) := 2 8
AXI_STREAM_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Signals
axisClk	sl
axisRst	sl := ' 0 '
txAxisMaster	AxiStreamMasterType
txAxisSlave	AxiStreamSlaveType
rxAxisMaster	AxiStreamMasterType
rxAxisSlave	AxiStreamSlaveType
rxAxisCtrl	AxiStreamCtrlType
axilClk	sl
axilRst	sl
uutAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
uutAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
uutAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
uutAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
srpAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
srpAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
srpAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
srpAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C

Instantiations
u_clkrst_axis	ClkRst <Entity ClkRst>
u_clkrst_axil	ClkRst <Entity ClkRst>
u_axilitesrpv0	AxiLiteSrpV0 <Entity AxiLiteSrpV0>
u_srpv0axilite_1	SrpV0AxiLite <Entity SrpV0AxiLite>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_clkrst_axis	ClkRst <Entity ClkRst>
u_clkrst_axil	ClkRst <Entity ClkRst>
u_axilitesrpv0	AxiLiteSrpV0 <Entity AxiLiteSrpV0>
u_srpv0axilite_1	SrpV0AxiLite <Entity SrpV0AxiLite>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>

The documentation for this design unit was generated from the following files:

Processes

Constants