AxiLiteRamSyncStatusVector.mapping Architecture Reference

Architecture >> AxiLiteRamSyncStatusVector::mapping

Processes
PROCESS_3	( axilRst , r , statusCnt )
seq	( axilClk , axilRst )
PROCESS_76	( axilRst , r , statusCnt )
seq	( axilClk , axilRst )

Constants
ADDR_WIDTH_C	positive := bitSize ( WIDTH_G- 1 )
REG_INIT_C	RegType := ( we = > ' 0 ' , addr = > ( others = > ' 0 ' ) , data = > ( others = > ' 0 ' ) , cnt = > 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
statusCnt	SlVectorArray ( WIDTH_G- 1 downto 0 , CNT_WIDTH_G- 1 downto 0 )

Records
RegType

Instantiations
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>
u_syncstatusvector	SyncStatusVector <Entity SyncStatusVector>
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>
u_syncstatusvector	SyncStatusVector <Entity SyncStatusVector>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd
• build/SRC_VHDL/surf/AxiLiteRamSyncStatusVector.vhd