AxiLiteRamSyncStatusVector Entity Reference

Inheritance diagram for AxiLiteRamSyncStatusVector:

Collaboration diagram for AxiLiteRamSyncStatusVector:

Entities
AxiLiteRamSyncStatusVector.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
READ_LATENCY_G	natural range 0 to 3 := 3
COMMON_CLK_G	boolean := false
IN_POLARITY_G	slv := " 1 "
OUT_POLARITY_G	sl := ' 1 '
SYNTH_CNT_G	slv := " 1 "
CNT_RST_EDGE_G	boolean := true
CNT_WIDTH_G	positive range 1 to 32 := 32
WIDTH_G	positive

Ports
wrClk	in	sl
wrRst	in	sl := ' 0 '
statusIn	in	slv ( WIDTH_G- 1 downto 0 )
statusOut	out	slv ( WIDTH_G- 1 downto 0 )
cntRstIn	in	sl := ' 0 '
rollOverEnIn	in	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd
• build/SRC_VHDL/surf/AxiLiteRamSyncStatusVector.vhd