AxiLiteMasterProxyIpIntegrator.rtl Architecture Reference

Architecture >> AxiLiteMasterProxyIpIntegrator::rtl

Signals
sAxiAResetN	sl := ' 1 '
sAxiReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
sAxiReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
sAxiWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
sAxiWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
mAxiReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
mAxiReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
mAxiWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
mAxiWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_slaveshimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_masterreadshimlayer	MasterAxiLiteIpIntegrator <Entity MasterAxiLiteIpIntegrator>
u_dut	AxiLiteMasterProxy <Entity AxiLiteMasterProxy>

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteMasterProxyIpIntegrator.vhd