AxiLiteMasterProxy Entity Reference

Inheritance diagram for AxiLiteMasterProxy:

Collaboration diagram for AxiLiteMasterProxy:

Entities
AxiLiteMasterProxy.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Ports
axiClk	in	sl
axiRst	in	sl
sAxiReadMaster	in	AxiLiteReadMasterType
sAxiReadSlave	out	AxiLiteReadSlaveType
sAxiWriteMaster	in	AxiLiteWriteMasterType
sAxiWriteSlave	out	AxiLiteWriteSlaveType
mAxiReadMaster	out	AxiLiteReadMasterType
mAxiReadSlave	in	AxiLiteReadSlaveType
mAxiWriteMaster	out	AxiLiteWriteMasterType
mAxiWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteMasterProxy.vhd
• build/SRC_VHDL/surf/AxiLiteMasterProxy.vhd