Architecture >> AxiLiteCrossbarI2cMux::mapping

Processes
comb	( ack , axilReadMaster , axilRst , axilWriteMaster , i2cRegMasterOut , r )
seq	( axilClk )
comb	( ack , axilReadMaster , axilRst , axilWriteMaster , i2cRegMasterOut , r )
seq	( axilClk )

Constants
I2C_SCL_5xFREQ_C	*real := 5 . 0 I2C_SCL_FREQ_G**
PRESCALE_C	natural := ( getTimeRatio ( AXIL_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C	*natural := natural ( AXIL_CLK_FREQ_G I2C_MIN_PULSE_G ) + 1**
DEVICE_MAP_C	I2cAxiLiteDevType := ( MakeI2cAxiLiteDevType ( i2cAddress = > I2C_MUX_ADDR_G , dataSize = > 8 , addrSize = > 0 , endianness = > ' 0 ' , repeatStart = > ' 0 ' ) )
I2C_MUX_INIT_C	I2cRegMasterInType := ( i2cAddr = > DEVICE_MAP_C.i2cAddress , tenbit = > DEVICE_MAP_C.i2cTenbit , regAddr = > ( others = > ' 0 ' ) , regWrData = > ( others = > ' 0 ' ) , regOp = > ' 1 ' , regAddrSkip = > ' 1 ' , regAddrSize = > ( others = > ' 0 ' ) , regDataSize = > ( others = > ' 0 ' ) , regReq = > ' 0 ' , busReq = > ' 0 ' , endianness = > DEVICE_MAP_C.endianness , repeatStart = > DEVICE_MAP_C.repeatStart , wrDataOnRd = > ' 0 ' )
REG_INIT_C	RegType := ( cnt = > 0 , i2cRstL = > ' 1 ' , rnw = > ' 0 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , i2cRegMasterIn = > I2C_MUX_INIT_C , req = > AXI_LITE_REQ_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , RST_S , MUX_S , XBAR_S )

Records
RegType

Instantiations
u_axilitemasterproxy	AxiLiteMasterProxy <Entity AxiLiteMasterProxy>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>
u_xbaraxilmaster	AxiLiteMaster <Entity AxiLiteMaster>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axilitemasterproxy	AxiLiteMasterProxy <Entity AxiLiteMasterProxy>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>
u_xbaraxilmaster	AxiLiteMaster <Entity AxiLiteMaster>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>

The documentation for this design unit was generated from the following files:

Processes

Constants