AxiLiteCrossbarI2cMux Entity Reference

Inheritance diagram for AxiLiteCrossbarI2cMux:

Collaboration diagram for AxiLiteCrossbarI2cMux:

Entities
AxiLiteCrossbarI2cMux.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
I2cPkg	Package <I2cPkg>
I2cMuxPkg	Package <I2cMuxPkg>

Generics
TPD_G	time := 1 ns
AXIL_PROXY_G	boolean := false
MUX_DECODE_MAP_G	Slv8Array := I2C_MUX_DECODE_MAP_TCA9548_C
I2C_MUX_ADDR_G	slv ( 6 downto 0 ) := b " 1110_000 "
I2C_SCL_FREQ_G	real := 400 . 0E + 3
I2C_MIN_PULSE_G	real := 100 . 0E - 9
AXIL_CLK_FREQ_G	real := 156 . 25E + 6
NUM_MASTER_SLOTS_G	natural range 1 to 64 := 4
DEC_ERROR_RESP_G	slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
MASTERS_CONFIG_G	AxiLiteCrossbarMasterConfigArray := AXIL_XBAR_CFG_DEFAULT_C
DEBUG_G	boolean := false

Ports
axilClk	in	sl
axilRst	in	sl
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
mAxilWriteMasters	out	AxiLiteWriteMasterArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxilWriteSlaves	in	AxiLiteWriteSlaveArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxilReadMasters	out	AxiLiteReadMasterArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxilReadSlaves	in	AxiLiteReadSlaveArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
i2cRst	out	sl
i2cRstL	out	sl
i2ci	in	i2c_in_type
i2co	out	i2c_out_type

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiLiteCrossbarI2cMux.vhd
• protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd