AxiI2cRegMasterCore.mapping Architecture Reference

Architecture >> AxiI2cRegMasterCore::mapping

Constants
I2C_SCL_5xFREQ_C	real := 5 . 0 * I2C_SCL_FREQ_G
PRESCALE_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C	natural := natural ( AXI_CLK_FREQ_G* I2C_MIN_PULSE_G ) + 1

Signals
i2cRegMasterIn	I2cRegMasterInType
i2cRegMasterOut	I2cRegMasterOutType
proxyReadMaster	AxiLiteReadMasterType
proxyReadSlave	AxiLiteReadSlaveType
proxyWriteMaster	AxiLiteWriteMasterType
proxyWriteSlave	AxiLiteWriteSlaveType

Instantiations
u_axilitemasterproxy	AxiLiteMasterProxy <Entity AxiLiteMasterProxy>
u_i2cregmasteraxibridge	I2cRegMasterAxiBridge <Entity I2cRegMasterAxiBridge>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>
u_axilitemasterproxy	AxiLiteMasterProxy <Entity AxiLiteMasterProxy>
u_i2cregmasteraxibridge	I2cRegMasterAxiBridge <Entity I2cRegMasterAxiBridge>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiI2cRegMasterCore.vhd
• protocols/i2c/axi/AxiI2cRegMasterCore.vhd