AxiI2cRegMasterCore Entity Reference

Inheritance diagram for AxiI2cRegMasterCore:

Collaboration diagram for AxiI2cRegMasterCore:

Entities
AxiI2cRegMasterCore.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
I2cPkg	Package <I2cPkg>

Generics
TPD_G	time := 1 ns
AXIL_PROXY_G	boolean := false
DEVICE_MAP_G	I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C
I2C_SCL_FREQ_G	real := 100 . 0E + 3
I2C_MIN_PULSE_G	real := 100 . 0E - 9
AXI_CLK_FREQ_G	real := 156 . 25E + 6

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
sel	out	slv ( DEVICE_MAP_G ' length- 1 downto 0 )
i2ci	in	i2c_in_type
i2co	out	i2c_out_type

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiI2cRegMasterCore.vhd
• protocols/i2c/axi/AxiI2cRegMasterCore.vhd