Architecture >> AxiDualPortRamIpIntegrator::mapping

Signals
uOrWe	sl
intWe	sl
intWeByte	slv ( wordCount ( DATA_WIDTH , 8 ) - 1 downto 0 )
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType

Attributes
X_INTERFACE_INFO	string
X_INTERFACE_PARAMETER	string
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT CLK "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT EN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT WE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT RST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT ADDR "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT DIN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 RAM_PORT DOUT "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME RAM_PORT , " & " MEM_SIZE " & integer ' image ( 2 ** ADDR_WIDTH ) & " , " & " MEM_WIDTH " & integer ' image ( DATA_WIDTH ) & " , " & " MEM_ECC NONE , " & " MASTER_TYPE OTHER , " & " READ_LATENCY " & integer ' image ( READ_LATENCY )

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>

The documentation for this design unit was generated from the following files:

Signals

Attributes