AxiDualPortRamIpIntegrator Entity Reference

Inheritance diagram for AxiDualPortRamIpIntegrator:

Collaboration diagram for AxiDualPortRamIpIntegrator:

Entities
AxiDualPortRamIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
EN_ERROR_RESP	boolean := false
SYNTH_MODE	string := " inferred "
MEMORY_TYPE	string := " block "
MEMORY_INIT_FILE	string := " none "
MEMORY_INIT_PARAM	string := " 0 "
READ_LATENCY	natural range 0 to 3 := 3
AXI_WR_EN	boolean := true
SYS_WR_EN	boolean := false
SYS_BYTE_WR_EN	boolean := false
COMMON_CLK	boolean := false
ADDR_WIDTH	positive := 5
DATA_WIDTH	positive := 32

Ports
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S_AXI_AWADDR	in	std_logic_vector ( ADDR_WIDTH+ 1 downto 0 )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_AWVALID	in	std_logic
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_WVALID	in	std_logic
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic
S_AXI_ARADDR	in	std_logic_vector ( ADDR_WIDTH+ 1 downto 0 )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_ARVALID	in	std_logic
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic
CLK	in	std_logic := ' 0 '
EN	in	std_logic := ' 1 '
WE	in	std_logic_vector ( ( DATA_WIDTH/ 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
RST	in	std_logic := ' 0 '
ADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
DIN	in	std_logic_vector ( DATA_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
DOUT	out	std_logic_vector ( DATA_WIDTH- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd
• build/SRC_VHDL/surf/AxiDualPortRamIpIntegrator.vhd