AdcDdrCoreWrapper.rtl Architecture Reference

Architecture >> AdcDdrCoreWrapper::rtl

Signals
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxiAResetN	sl := ' 1 '
dataDelayWrite	AdcDdrDelayArray ( 1 downto 0 )
fcoDelayWrite	AdcDdrDelayArray ( 0 downto 0 )
sampleArray	Slv16Array ( 1 downto 0 )
streamArray	AxiStreamMasterArray ( 1 downto 0 )
bitSlipInt	slv ( 0 downto 0 )

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AdcDdrCore <Entity AdcDdrCore>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/wrappers/AdcDdrCoreWrapper.vhd