AdcDdrCoreWrapper Entity Reference

Inheritance diagram for AdcDdrCoreWrapper:

Collaboration diagram for AdcDdrCoreWrapper:

Entities
AdcDdrCoreWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
AdcDdrPkg	Package <AdcDdrPkg>

Generics
TPD_G	time := 1 ns
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 00000000 "
PATTERN_CHECK_G	boolean := true
NEGATE_G	boolean := false

Ports
axilClk	in	sl
axilRst	in	sl
S_AXI_AWADDR	in	slv ( 31 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 31 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
captureClk	in	sl
captureRst	in	sl
delayReady	in	sl := ' 0 '
fcoWord	in	slv ( 13 downto 0 )
fcoValid	in	sl
sampleValid	in	sl
sampleIn	in	slv ( 31 downto 0 )
bitSlip	out	sl
dataDelayValue	out	slv ( 31 downto 0 )
dataDelayLoad	out	slv ( 1 downto 0 )
fcoDelayValue	out	slv ( 15 downto 0 )
fcoDelayLoad	out	sl
phyReset	out	sl
streamClk	in	sl
streamRst	in	sl
streamValid	out	slv ( 1 downto 0 )
streamData	out	slv ( 31 downto 0 )
streamKeep	out	slv ( 3 downto 0 )
streamDest	out	slv ( 15 downto 0 )
streamLast	out	slv ( 1 downto 0 )
streamUser	out	slv ( 15 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/wrappers/AdcDdrCoreWrapper.vhd