SURF  1.0
mapping Architecture Reference

Components

TenGigEthGtx7Core 

Signals

mAxiReadMaster  AxiLiteReadMasterType
mAxiReadSlave  AxiLiteReadSlaveType
mAxiWriteMaster  AxiLiteWriteMasterType
mAxiWriteSlave  AxiLiteWriteSlaveType
phyRxd  slv ( 63 downto 0 )
phyRxc  slv ( 7 downto 0 )
phyTxd  slv ( 63 downto 0 )
phyTxc  slv ( 7 downto 0 )
areset  sl
txClk322  sl
txUsrClk  sl
txUsrClk2  sl
txUsrRdy  sl
drpReqGnt  sl
drpEn  sl
drpWe  sl
drpAddr  slv ( 15 downto 0 )
drpDi  slv ( 15 downto 0 )
drpRdy  sl
drpDo  slv ( 15 downto 0 )
configurationVector  slv ( 535 downto 0 ) := ( others = > ' 0 ' )
config  TenGigEthConfig
status  TenGigEthStatus
macRxAxisMaster  AxiStreamMasterType
macRxAxisCtrl  AxiStreamCtrlType
macTxAxisMaster  AxiStreamMasterType
macTxAxisSlave  AxiStreamSlaveType

Instantiations

u_axiliteasync  AxiLiteAsync <Entity AxiLiteAsync>
u_sync  SynchronizerVector <Entity SynchronizerVector>
u_mac  EthMacTop <Entity EthMacTop>
u_tengigethgtx7core  tengigethgtx7core
u_tengigethrst  TenGigEthRst <Entity TenGigEthRst>
u_tengigethreg  TenGigEthReg <Entity TenGigEthReg>

Detailed Description

Definition at line 75 of file TenGigEthGtx7.vhd.

Member Data Documentation

◆ TenGigEthGtx7Core

TenGigEthGtx7Core
Component

Definition at line 77 of file TenGigEthGtx7.vhd.

◆ mAxiReadMaster

Definition at line 128 of file TenGigEthGtx7.vhd.

◆ mAxiReadSlave

Definition at line 129 of file TenGigEthGtx7.vhd.

◆ mAxiWriteMaster

Definition at line 130 of file TenGigEthGtx7.vhd.

◆ mAxiWriteSlave

Definition at line 131 of file TenGigEthGtx7.vhd.

◆ phyRxd

phyRxd slv ( 63 downto 0 )
Signal

Definition at line 133 of file TenGigEthGtx7.vhd.

◆ phyRxc

phyRxc slv ( 7 downto 0 )
Signal

Definition at line 134 of file TenGigEthGtx7.vhd.

◆ phyTxd

phyTxd slv ( 63 downto 0 )
Signal

Definition at line 135 of file TenGigEthGtx7.vhd.

◆ phyTxc

phyTxc slv ( 7 downto 0 )
Signal

Definition at line 136 of file TenGigEthGtx7.vhd.

◆ areset

areset sl
Signal

Definition at line 138 of file TenGigEthGtx7.vhd.

◆ txClk322

txClk322 sl
Signal

Definition at line 139 of file TenGigEthGtx7.vhd.

◆ txUsrClk

txUsrClk sl
Signal

Definition at line 140 of file TenGigEthGtx7.vhd.

◆ txUsrClk2

txUsrClk2 sl
Signal

Definition at line 141 of file TenGigEthGtx7.vhd.

◆ txUsrRdy

txUsrRdy sl
Signal

Definition at line 142 of file TenGigEthGtx7.vhd.

◆ drpReqGnt

drpReqGnt sl
Signal

Definition at line 144 of file TenGigEthGtx7.vhd.

◆ drpEn

drpEn sl
Signal

Definition at line 145 of file TenGigEthGtx7.vhd.

◆ drpWe

drpWe sl
Signal

Definition at line 146 of file TenGigEthGtx7.vhd.

◆ drpAddr

drpAddr slv ( 15 downto 0 )
Signal

Definition at line 147 of file TenGigEthGtx7.vhd.

◆ drpDi

drpDi slv ( 15 downto 0 )
Signal

Definition at line 148 of file TenGigEthGtx7.vhd.

◆ drpRdy

drpRdy sl
Signal

Definition at line 149 of file TenGigEthGtx7.vhd.

◆ drpDo

drpDo slv ( 15 downto 0 )
Signal

Definition at line 150 of file TenGigEthGtx7.vhd.

◆ configurationVector

configurationVector slv ( 535 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 152 of file TenGigEthGtx7.vhd.

◆ config

Definition at line 154 of file TenGigEthGtx7.vhd.

◆ status

Definition at line 155 of file TenGigEthGtx7.vhd.

◆ macRxAxisMaster

Definition at line 157 of file TenGigEthGtx7.vhd.

◆ macRxAxisCtrl

Definition at line 158 of file TenGigEthGtx7.vhd.

◆ macTxAxisMaster

Definition at line 159 of file TenGigEthGtx7.vhd.

◆ macTxAxisSlave

Definition at line 160 of file TenGigEthGtx7.vhd.

◆ u_axiliteasync

u_axiliteasync AxiLiteAsync
Instantiation

Definition at line 188 of file TenGigEthGtx7.vhd.

◆ u_sync

u_sync SynchronizerVector
Instantiation

Definition at line 205 of file TenGigEthGtx7.vhd.

◆ u_mac

u_mac EthMacTop
Instantiation

Definition at line 233 of file TenGigEthGtx7.vhd.

◆ u_tengigethgtx7core

u_tengigethgtx7core tengigethgtx7core
Instantiation

Definition at line 294 of file TenGigEthGtx7.vhd.

◆ u_tengigethrst

u_tengigethrst TenGigEthRst
Instantiation

Definition at line 316 of file TenGigEthGtx7.vhd.

◆ u_tengigethreg

u_tengigethreg TenGigEthReg
Instantiation

Definition at line 353 of file TenGigEthGtx7.vhd.


The documentation for this class was generated from the following file: