SURF  1.0
Constants | Types | Records | Signals | Processes | Instantiations
structure Architecture Reference

Processes

PROCESS_9  ( axiClk )
PROCESS_10  ( axiRst , ib , intReadMasters , intWriteMasters , ob , popFifoValid , r )
PROCESS_11  ( axiRst , ib , ibAck , popFifoPFull , pushFifoDout , pushFifoValid , r )
PROCESS_12  ( axiRst , ob , obAck , pushFifoDout , pushFifoValid , r )

Use Clauses

ibReq 
obReq 

Constants

PUSH_ADDR_WIDTH_C  integer := FREE_ADDR_WIDTH_G
POP_ADDR_WIDTH_C  integer := FREE_ADDR_WIDTH_G
POP_FIFO_PFULL_C  integer := ( 2 ** POP_ADDR_WIDTH_C ) - 10
POP_FIFO_COUNT_C  integer := 2
PUSH_FIFO_COUNT_C  integer := 2
IB_FIFO_C  integer := 0
OB_FIFO_C  integer := 1
CROSSBAR_CONN_C  slv ( 15 downto 0 ) := x " FFFF "
LOC_INDEX_C  natural := 0
LOC_BASE_ADDR_C  slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 000 "
LOC_NUM_BITS_C  natural := 10
FIFO_INDEX_C  natural := 1
FIFO_BASE_ADDR_C  slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 400 "
FIFO_NUM_BITS_C  natural := 10
AXI_CROSSBAR_MASTERS_CONFIG_C  AxiLiteCrossbarMasterConfigArray ( 1 downto 0 ) := ( LOC_INDEX_C = > ( baseAddr = > LOC_BASE_ADDR_C , addrBits = > LOC_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) , FIFO_INDEX_C = > ( baseAddr = > FIFO_BASE_ADDR_C , addrBits = > FIFO_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) )
REG_INIT_C  RegType := ( maxRxSize = > ( others = > ' 0 ' ) , interrupt = > ' 0 ' , intEnable = > ' 0 ' , intAck = > ' 0 ' , acknowledge = > ' 0 ' , online = > ' 0 ' , rxEnable = > ' 0 ' , txEnable = > ' 0 ' , fifoClear = > ' 1 ' , swCache = > AXI_CACHE_G , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )
IB_INIT_C  IbType := ( state = > IDLE_S , intPending = > ' 0 ' , ibReq = > AXI_WRITE_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )
OB_INIT_C  ObType := ( state = > IDLE_S , intPending = > ' 0 ' , obReq = > AXI_READ_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )

Types

StateType ( IDLE_S , WAIT_S , FIFO_0_S , FIFO_1_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
ib  IbType := IB_INIT_C
ibin  IbType
ob  ObType := OB_INIT_C
obin  ObType
intReadMasters  AxiLiteReadMasterArray ( 1 downto 0 )
intReadSlaves  AxiLiteReadSlaveArray ( 1 downto 0 )
intWriteMasters  AxiLiteWriteMasterArray ( 1 downto 0 )
intWriteSlaves  AxiLiteWriteSlaveArray ( 1 downto 0 )
popFifoClk  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
popFifoRst  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
popFifoValid  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
popFifoWrite  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
popFifoPFull  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
popFifoDin  Slv32Array ( POP_FIFO_COUNT_C - 1 downto 0 )
pushFifoClk  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
pushFifoRst  slv ( POP_FIFO_COUNT_C - 1 downto 0 )
pushFifoValid  slv ( PUSH_FIFO_COUNT_C - 1 downto 0 )
pushFifoDout  Slv36Array ( PUSH_FIFO_COUNT_C - 1 downto 0 )
pushFifoRead  slv ( PUSH_FIFO_COUNT_C - 1 downto 0 )
obAck  AxiReadDmaAckType
ibAck  AxiWriteDmaAckType

Records

RegType  
maxRxSize  slv ( 23 downto 0 )
interrupt  sl
intEnable  sl
intAck  sl
acknowledge  sl
online  sl
rxEnable  sl
txEnable  sl
fifoClear  sl
swCache  slv ( 3 downto 0 )
axiReadSlave  AxiLiteReadSlaveType
axiWriteSlave  AxiLiteWriteSlaveType
IbType  
state  StateType
intPending  sl
popFifoWrite  sl
popFifoDin  slv ( 31 downto 0 )
pushFifoRead  sl
ObType  

Instantiations

u_axicrossbar  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_swfifos  AxiLiteFifoPushPop <Entity AxiLiteFifoPushPop>
u_ibdma  AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_obdma  AxiStreamDmaRead <Entity AxiStreamDmaRead>

Detailed Description

Definition at line 72 of file AxiStreamDma.vhd.

Member Function Documentation

◆ PROCESS_9()

PROCESS_9 (   axiClk  
)
Process

Definition at line 215 of file AxiStreamDma.vhd.

◆ PROCESS_10()

PROCESS_10 (   axiRst,
  ib,
  intReadMasters,
  intWriteMasters,
  ob,
  popFifoValid,
  r 
)

Definition at line 306 of file AxiStreamDma.vhd.

◆ PROCESS_11()

PROCESS_11 (   axiRst,
  ib,
  ibAck,
  popFifoPFull,
  pushFifoDout,
  pushFifoValid,
  r 
)

Definition at line 423 of file AxiStreamDma.vhd.

◆ PROCESS_12()

PROCESS_12 (   axiRst,
  ob,
  obAck,
  pushFifoDout,
  pushFifoValid,
  r 
)

Definition at line 518 of file AxiStreamDma.vhd.

Member Data Documentation

◆ PUSH_ADDR_WIDTH_C

PUSH_ADDR_WIDTH_C integer := FREE_ADDR_WIDTH_G
Constant

Definition at line 74 of file AxiStreamDma.vhd.

◆ POP_ADDR_WIDTH_C

POP_ADDR_WIDTH_C integer := FREE_ADDR_WIDTH_G
Constant

Definition at line 75 of file AxiStreamDma.vhd.

◆ POP_FIFO_PFULL_C

POP_FIFO_PFULL_C integer := ( 2 ** POP_ADDR_WIDTH_C ) - 10
Constant

Definition at line 77 of file AxiStreamDma.vhd.

◆ POP_FIFO_COUNT_C

POP_FIFO_COUNT_C integer := 2
Constant

Definition at line 79 of file AxiStreamDma.vhd.

◆ PUSH_FIFO_COUNT_C

PUSH_FIFO_COUNT_C integer := 2
Constant

Definition at line 80 of file AxiStreamDma.vhd.

◆ IB_FIFO_C

IB_FIFO_C integer := 0
Constant

Definition at line 82 of file AxiStreamDma.vhd.

◆ OB_FIFO_C

OB_FIFO_C integer := 1
Constant

Definition at line 83 of file AxiStreamDma.vhd.

◆ CROSSBAR_CONN_C

CROSSBAR_CONN_C slv ( 15 downto 0 ) := x " FFFF "
Constant

Definition at line 85 of file AxiStreamDma.vhd.

◆ LOC_INDEX_C

LOC_INDEX_C natural := 0
Constant

Definition at line 87 of file AxiStreamDma.vhd.

◆ LOC_BASE_ADDR_C

LOC_BASE_ADDR_C slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 000 "
Constant

Definition at line 88 of file AxiStreamDma.vhd.

◆ LOC_NUM_BITS_C

LOC_NUM_BITS_C natural := 10
Constant

Definition at line 89 of file AxiStreamDma.vhd.

◆ FIFO_INDEX_C

FIFO_INDEX_C natural := 1
Constant

Definition at line 91 of file AxiStreamDma.vhd.

◆ FIFO_BASE_ADDR_C

FIFO_BASE_ADDR_C slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 400 "
Constant

Definition at line 92 of file AxiStreamDma.vhd.

◆ FIFO_NUM_BITS_C

FIFO_NUM_BITS_C natural := 10
Constant

Definition at line 93 of file AxiStreamDma.vhd.

◆ AXI_CROSSBAR_MASTERS_CONFIG_C

AXI_CROSSBAR_MASTERS_CONFIG_C AxiLiteCrossbarMasterConfigArray ( 1 downto 0 ) := ( LOC_INDEX_C = > ( baseAddr = > LOC_BASE_ADDR_C , addrBits = > LOC_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) , FIFO_INDEX_C = > ( baseAddr = > FIFO_BASE_ADDR_C , addrBits = > FIFO_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) )
Constant

Definition at line 95 of file AxiStreamDma.vhd.

◆ StateType

StateType ( IDLE_S , WAIT_S , FIFO_0_S , FIFO_1_S )
Type

Definition at line 105 of file AxiStreamDma.vhd.

◆ RegType

RegType
Record

Definition at line 111 of file AxiStreamDma.vhd.

◆ maxRxSize

maxRxSize slv ( 23 downto 0 )
Record

Definition at line 112 of file AxiStreamDma.vhd.

◆ interrupt

interrupt sl
Record

Definition at line 113 of file AxiStreamDma.vhd.

◆ intEnable

intEnable sl
Record

Definition at line 114 of file AxiStreamDma.vhd.

◆ intAck

intAck sl
Record

Definition at line 115 of file AxiStreamDma.vhd.

◆ acknowledge

acknowledge sl
Record

Definition at line 116 of file AxiStreamDma.vhd.

◆ online

online sl
Record

Definition at line 117 of file AxiStreamDma.vhd.

◆ rxEnable

rxEnable sl
Record

Definition at line 118 of file AxiStreamDma.vhd.

◆ txEnable

txEnable sl
Record

Definition at line 119 of file AxiStreamDma.vhd.

◆ fifoClear

fifoClear sl
Record

Definition at line 120 of file AxiStreamDma.vhd.

◆ swCache

swCache slv ( 3 downto 0 )
Record

Definition at line 121 of file AxiStreamDma.vhd.

◆ axiReadSlave

axiReadSlave AxiLiteReadSlaveType
Record

Definition at line 122 of file AxiStreamDma.vhd.

◆ axiWriteSlave

axiWriteSlave AxiLiteWriteSlaveType
Record

Definition at line 123 of file AxiStreamDma.vhd.

◆ REG_INIT_C

REG_INIT_C RegType := ( maxRxSize = > ( others = > ' 0 ' ) , interrupt = > ' 0 ' , intEnable = > ' 0 ' , intAck = > ' 0 ' , acknowledge = > ' 0 ' , online = > ' 0 ' , rxEnable = > ' 0 ' , txEnable = > ' 0 ' , fifoClear = > ' 1 ' , swCache = > AXI_CACHE_G , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )
Constant

Definition at line 126 of file AxiStreamDma.vhd.

◆ r

r RegType := REG_INIT_C
Signal

Definition at line 140 of file AxiStreamDma.vhd.

◆ rin

rin RegType
Signal

Definition at line 141 of file AxiStreamDma.vhd.

◆ IbType

IbType
Record

Definition at line 143 of file AxiStreamDma.vhd.

◆ state

state StateType
Record

Definition at line 144 of file AxiStreamDma.vhd.

◆ intPending

intPending sl
Record

Definition at line 145 of file AxiStreamDma.vhd.

◆ ibReq

ibReq
Package

Definition at line 146 of file AxiStreamDma.vhd.

◆ popFifoWrite [1/2]

popFifoWrite sl
Record

Definition at line 147 of file AxiStreamDma.vhd.

◆ popFifoDin [1/2]

popFifoDin slv ( 31 downto 0 )
Record

Definition at line 148 of file AxiStreamDma.vhd.

◆ pushFifoRead [1/2]

pushFifoRead sl
Record

Definition at line 149 of file AxiStreamDma.vhd.

◆ IB_INIT_C

IB_INIT_C IbType := ( state = > IDLE_S , intPending = > ' 0 ' , ibReq = > AXI_WRITE_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )
Constant

Definition at line 152 of file AxiStreamDma.vhd.

◆ ib

ib IbType := IB_INIT_C
Signal

Definition at line 160 of file AxiStreamDma.vhd.

◆ ibin

ibin IbType
Signal

Definition at line 161 of file AxiStreamDma.vhd.

◆ ObType

ObType
Record

Definition at line 163 of file AxiStreamDma.vhd.

◆ obReq

obReq
Package

Definition at line 166 of file AxiStreamDma.vhd.

◆ OB_INIT_C

OB_INIT_C ObType := ( state = > IDLE_S , intPending = > ' 0 ' , obReq = > AXI_READ_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )
Constant

Definition at line 172 of file AxiStreamDma.vhd.

◆ ob

ob ObType := OB_INIT_C
Signal

Definition at line 180 of file AxiStreamDma.vhd.

◆ obin

obin ObType
Signal

Definition at line 181 of file AxiStreamDma.vhd.

◆ intReadMasters

intReadMasters AxiLiteReadMasterArray ( 1 downto 0 )
Signal

Definition at line 183 of file AxiStreamDma.vhd.

◆ intReadSlaves

intReadSlaves AxiLiteReadSlaveArray ( 1 downto 0 )
Signal

Definition at line 184 of file AxiStreamDma.vhd.

◆ intWriteMasters

intWriteMasters AxiLiteWriteMasterArray ( 1 downto 0 )
Signal

Definition at line 185 of file AxiStreamDma.vhd.

◆ intWriteSlaves

intWriteSlaves AxiLiteWriteSlaveArray ( 1 downto 0 )
Signal

Definition at line 186 of file AxiStreamDma.vhd.

◆ popFifoClk

popFifoClk slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 188 of file AxiStreamDma.vhd.

◆ popFifoRst

popFifoRst slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 189 of file AxiStreamDma.vhd.

◆ popFifoValid

popFifoValid slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 190 of file AxiStreamDma.vhd.

◆ popFifoWrite [2/2]

popFifoWrite slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 191 of file AxiStreamDma.vhd.

◆ popFifoPFull

popFifoPFull slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 192 of file AxiStreamDma.vhd.

◆ popFifoDin [2/2]

popFifoDin Slv32Array ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 193 of file AxiStreamDma.vhd.

◆ pushFifoClk

pushFifoClk slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 194 of file AxiStreamDma.vhd.

◆ pushFifoRst

pushFifoRst slv ( POP_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 195 of file AxiStreamDma.vhd.

◆ pushFifoValid

pushFifoValid slv ( PUSH_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 196 of file AxiStreamDma.vhd.

◆ pushFifoDout

pushFifoDout Slv36Array ( PUSH_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 197 of file AxiStreamDma.vhd.

◆ pushFifoRead [2/2]

pushFifoRead slv ( PUSH_FIFO_COUNT_C - 1 downto 0 )
Signal

Definition at line 198 of file AxiStreamDma.vhd.

◆ obAck

obAck AxiReadDmaAckType
Signal

Definition at line 200 of file AxiStreamDma.vhd.

◆ ibAck

ibAck AxiWriteDmaAckType
Signal

Definition at line 202 of file AxiStreamDma.vhd.

◆ u_axicrossbar

u_axicrossbar AxiLiteCrossbar
Instantiation

Definition at line 243 of file AxiStreamDma.vhd.

◆ u_swfifos

u_swfifos AxiLiteFifoPushPop
Instantiation

Definition at line 294 of file AxiStreamDma.vhd.

◆ u_ibdma

u_ibdma AxiStreamDmaWrite
Instantiation

Definition at line 421 of file AxiStreamDma.vhd.

◆ u_obdma

u_obdma AxiStreamDmaRead
Instantiation

Definition at line 516 of file AxiStreamDma.vhd.

The documentation for this class was generated from the following file: