SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiStreamDma Entity Reference
axi
+ Inheritance diagram for AxiStreamDma:
+ Collaboration diagram for AxiStreamDma:

Entities

structure  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiPkg  Package <AxiPkg>
AxiDmaPkg  Package <AxiDmaPkg>

Generics

TPD_G  time := 1 ns
FREE_ADDR_WIDTH_G  integer := 9
AXIL_COUNT_G  integer range 1 to 2 := 1
AXIL_BASE_ADDR_G  slv ( 31 downto 0 ) := x " 00000000 "
AXI_READY_EN_G  boolean := false
AXIS_READY_EN_G  boolean := false
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C
AXI_BURST_G  slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G  slv ( 3 downto 0 ) := " 1111 "
PEND_THRESH_G  natural := 0
BYP_SHIFT_G  boolean := false

Ports

axiClk   in sl
axiRst   in sl
axilReadMaster   in AxiLiteReadMasterArray ( AXIL_COUNT_G - 1 downto 0 )
axilReadSlave   out AxiLiteReadSlaveArray ( AXIL_COUNT_G - 1 downto 0 )
axilWriteMaster   in AxiLiteWriteMasterArray ( AXIL_COUNT_G - 1 downto 0 )
axilWriteSlave   out AxiLiteWriteSlaveArray ( AXIL_COUNT_G - 1 downto 0 )
interrupt   out sl
online   out sl
acknowledge   out sl
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
mAxisCtrl   in AxiStreamCtrlType
axiReadMaster   out AxiReadMasterType
axiReadSlave   in AxiReadSlaveType
axiWriteMaster   out AxiWriteMasterType
axiWriteSlave   in AxiWriteSlaveType
axiWriteCtrl   in AxiCtrlType

Detailed Description

See also
entity

Definition at line 32 of file AxiStreamDma.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file AxiStreamDma.vhd.

◆ FREE_ADDR_WIDTH_G

FREE_ADDR_WIDTH_G integer := 9
Generic

Definition at line 35 of file AxiStreamDma.vhd.

◆ AXIL_COUNT_G

AXIL_COUNT_G integer range 1 to 2 := 1
Generic

Definition at line 36 of file AxiStreamDma.vhd.

◆ AXIL_BASE_ADDR_G

AXIL_BASE_ADDR_G slv ( 31 downto 0 ) := x " 00000000 "
Generic

Definition at line 37 of file AxiStreamDma.vhd.

◆ AXI_READY_EN_G

AXI_READY_EN_G boolean := false
Generic

Definition at line 38 of file AxiStreamDma.vhd.

◆ AXIS_READY_EN_G

AXIS_READY_EN_G boolean := false
Generic

Definition at line 39 of file AxiStreamDma.vhd.

◆ AXIS_CONFIG_G

AXIS_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 40 of file AxiStreamDma.vhd.

◆ AXI_CONFIG_G

AXI_CONFIG_G AxiConfigType := AXI_CONFIG_INIT_C
Generic

Definition at line 41 of file AxiStreamDma.vhd.

◆ AXI_BURST_G

AXI_BURST_G slv ( 1 downto 0 ) := " 01 "
Generic

Definition at line 42 of file AxiStreamDma.vhd.

◆ AXI_CACHE_G

AXI_CACHE_G slv ( 3 downto 0 ) := " 1111 "
Generic

Definition at line 43 of file AxiStreamDma.vhd.

◆ PEND_THRESH_G

PEND_THRESH_G natural := 0
Generic

Definition at line 44 of file AxiStreamDma.vhd.

◆ BYP_SHIFT_G

BYP_SHIFT_G boolean := false
Generic

Definition at line 45 of file AxiStreamDma.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 48 of file AxiStreamDma.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 49 of file AxiStreamDma.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterArray ( AXIL_COUNT_G - 1 downto 0 )
Port

Definition at line 51 of file AxiStreamDma.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveArray ( AXIL_COUNT_G - 1 downto 0 )
Port

Definition at line 52 of file AxiStreamDma.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterArray ( AXIL_COUNT_G - 1 downto 0 )
Port

Definition at line 53 of file AxiStreamDma.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveArray ( AXIL_COUNT_G - 1 downto 0 )
Port

Definition at line 54 of file AxiStreamDma.vhd.

◆ interrupt

interrupt out sl
Port

Definition at line 55 of file AxiStreamDma.vhd.

◆ online

online out sl
Port

Definition at line 56 of file AxiStreamDma.vhd.

◆ acknowledge

acknowledge out sl
Port

Definition at line 57 of file AxiStreamDma.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 59 of file AxiStreamDma.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 60 of file AxiStreamDma.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 61 of file AxiStreamDma.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 62 of file AxiStreamDma.vhd.

◆ mAxisCtrl

mAxisCtrl in AxiStreamCtrlType
Port

Definition at line 63 of file AxiStreamDma.vhd.

◆ axiReadMaster

axiReadMaster out AxiReadMasterType
Port

Definition at line 65 of file AxiStreamDma.vhd.

◆ axiReadSlave

axiReadSlave in AxiReadSlaveType
Port

Definition at line 66 of file AxiStreamDma.vhd.

◆ axiWriteMaster

axiWriteMaster out AxiWriteMasterType
Port

Definition at line 67 of file AxiStreamDma.vhd.

◆ axiWriteSlave

axiWriteSlave in AxiWriteSlaveType
Port

Definition at line 68 of file AxiStreamDma.vhd.

◆ axiWriteCtrl

axiWriteCtrl in AxiCtrlType
Port

Definition at line 69 of file AxiStreamDma.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file AxiStreamDma.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file AxiStreamDma.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiStreamDma.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 22 of file AxiStreamDma.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file AxiStreamDma.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 25 of file AxiStreamDma.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file AxiStreamDma.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 27 of file AxiStreamDma.vhd.

◆ AxiDmaPkg

AxiDmaPkg
Package

Definition at line 28 of file AxiStreamDma.vhd.

The documentation for this class was generated from the following file: