SURF  1.0
AxiStreamDmaWrite Entity Reference
+ Inheritance diagram for AxiStreamDmaWrite:
+ Collaboration diagram for AxiStreamDmaWrite:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiPkg  Package <AxiPkg>
AxiDmaPkg  Package <AxiDmaPkg>

Generics

TPD_G  time := 1 ns
AXI_READY_EN_G  boolean := false
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C
AXI_BURST_G  slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G  slv ( 3 downto 0 ) := " 1111 "
SW_CACHE_EN_G  boolean := false
ACK_WAIT_BVALID_G  boolean := true
PIPE_STAGES_G  natural := 1
BYP_SHIFT_G  boolean := false
BYP_CACHE_G  boolean := false

Ports

axiClk   in sl
axiRst   in sl
dmaReq   in AxiWriteDmaReqType
dmaAck   out AxiWriteDmaAckType
swCache   in slv ( 3 downto 0 ) := " 0000 "
axisMaster   in AxiStreamMasterType
axisSlave   out AxiStreamSlaveType
axiWriteMaster   out AxiWriteMasterType
axiWriteSlave   in AxiWriteSlaveType
axiWriteCtrl   in AxiCtrlType := AXI_CTRL_UNUSED_C

Detailed Description

See also
entity

Definition at line 32 of file AxiStreamDmaWrite.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file AxiStreamDmaWrite.vhd.

◆ AXI_READY_EN_G

AXI_READY_EN_G boolean := false
Generic

Definition at line 35 of file AxiStreamDmaWrite.vhd.

◆ AXIS_CONFIG_G

◆ AXI_CONFIG_G

Definition at line 37 of file AxiStreamDmaWrite.vhd.

◆ AXI_BURST_G

AXI_BURST_G slv ( 1 downto 0 ) := " 01 "
Generic

Definition at line 38 of file AxiStreamDmaWrite.vhd.

◆ AXI_CACHE_G

AXI_CACHE_G slv ( 3 downto 0 ) := " 1111 "
Generic

Definition at line 39 of file AxiStreamDmaWrite.vhd.

◆ SW_CACHE_EN_G

SW_CACHE_EN_G boolean := false
Generic

Definition at line 40 of file AxiStreamDmaWrite.vhd.

◆ ACK_WAIT_BVALID_G

ACK_WAIT_BVALID_G boolean := true
Generic

Definition at line 41 of file AxiStreamDmaWrite.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural := 1
Generic

Definition at line 42 of file AxiStreamDmaWrite.vhd.

◆ BYP_SHIFT_G

BYP_SHIFT_G boolean := false
Generic

Definition at line 43 of file AxiStreamDmaWrite.vhd.

◆ BYP_CACHE_G

BYP_CACHE_G boolean := false
Generic

Definition at line 44 of file AxiStreamDmaWrite.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiStreamDmaWrite.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiStreamDmaWrite.vhd.

◆ dmaReq

Definition at line 50 of file AxiStreamDmaWrite.vhd.

◆ dmaAck

Definition at line 51 of file AxiStreamDmaWrite.vhd.

◆ swCache

swCache in slv ( 3 downto 0 ) := " 0000 "
Port

Definition at line 52 of file AxiStreamDmaWrite.vhd.

◆ axisMaster

Definition at line 54 of file AxiStreamDmaWrite.vhd.

◆ axisSlave

Definition at line 55 of file AxiStreamDmaWrite.vhd.

◆ axiWriteMaster

Definition at line 57 of file AxiStreamDmaWrite.vhd.

◆ axiWriteSlave

Definition at line 58 of file AxiStreamDmaWrite.vhd.

◆ axiWriteCtrl

Definition at line 59 of file AxiStreamDmaWrite.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiStreamDmaWrite.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiStreamDmaWrite.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file AxiStreamDmaWrite.vhd.

◆ std_logic_unsigned

Definition at line 23 of file AxiStreamDmaWrite.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 25 of file AxiStreamDmaWrite.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 26 of file AxiStreamDmaWrite.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 27 of file AxiStreamDmaWrite.vhd.

◆ AxiDmaPkg

AxiDmaPkg
Package

Definition at line 28 of file AxiStreamDmaWrite.vhd.


The documentation for this class was generated from the following file: