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SURF
1.0
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Inheritance diagram for AxiStreamDmaWrite:
Collaboration diagram for AxiStreamDmaWrite:Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
| AxiPkg | Package <AxiPkg> |
| AxiDmaPkg | Package <AxiDmaPkg> |
Generics | |
| TPD_G | time := 1 ns |
| AXI_READY_EN_G | boolean := false |
| AXIS_CONFIG_G | AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C |
| AXI_CONFIG_G | AxiConfigType := AXI_CONFIG_INIT_C |
| AXI_BURST_G | slv ( 1 downto 0 ) := " 01 " |
| AXI_CACHE_G | slv ( 3 downto 0 ) := " 1111 " |
| SW_CACHE_EN_G | boolean := false |
| ACK_WAIT_BVALID_G | boolean := true |
| PIPE_STAGES_G | natural := 1 |
| BYP_SHIFT_G | boolean := false |
| BYP_CACHE_G | boolean := false |
Ports | |
| axiClk | in sl |
| axiRst | in sl |
| dmaReq | in AxiWriteDmaReqType |
| dmaAck | out AxiWriteDmaAckType |
| swCache | in slv ( 3 downto 0 ) := " 0000 " |
| axisMaster | in AxiStreamMasterType |
| axisSlave | out AxiStreamSlaveType |
| axiWriteMaster | out AxiWriteMasterType |
| axiWriteSlave | in AxiWriteSlaveType |
| axiWriteCtrl | in AxiCtrlType := AXI_CTRL_UNUSED_C |
Definition at line 32 of file AxiStreamDmaWrite.vhd.
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Generic |
Definition at line 34 of file AxiStreamDmaWrite.vhd.
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Generic |
Definition at line 35 of file AxiStreamDmaWrite.vhd.
Definition at line 36 of file AxiStreamDmaWrite.vhd.
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Generic |
Definition at line 37 of file AxiStreamDmaWrite.vhd.
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Definition at line 38 of file AxiStreamDmaWrite.vhd.
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Definition at line 39 of file AxiStreamDmaWrite.vhd.
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Generic |
Definition at line 40 of file AxiStreamDmaWrite.vhd.
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Definition at line 41 of file AxiStreamDmaWrite.vhd.
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Definition at line 42 of file AxiStreamDmaWrite.vhd.
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Definition at line 43 of file AxiStreamDmaWrite.vhd.
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Generic |
Definition at line 44 of file AxiStreamDmaWrite.vhd.
Definition at line 47 of file AxiStreamDmaWrite.vhd.
Definition at line 48 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 50 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 51 of file AxiStreamDmaWrite.vhd.
Definition at line 52 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 54 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 55 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 57 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 58 of file AxiStreamDmaWrite.vhd.
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Port |
Definition at line 59 of file AxiStreamDmaWrite.vhd.
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Library |
Definition at line 20 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 21 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 22 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 23 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 25 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 26 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 27 of file AxiStreamDmaWrite.vhd.
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Package |
Definition at line 28 of file AxiStreamDmaWrite.vhd.