surf_1_documentation/html/GLinkGtp7FixedLat_8vhd_source.html

 -------------------------------------------------------------------------------
 -- File       : GLinkGtp7FixedLat.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2014-01-30
 -- Last update: 2017-05-08
 -------------------------------------------------------------------------------
 -- Description: G-Link wrapper for GTP7 transceiver
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
 -- top-level directory of this distribution and at:
 --    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
 -- No part of 'SLAC Firmware Standard Library', including this file,
 -- may be copied, modified, propagated, or distributed except according to
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 use work.StdRtlPkg.all;
 use work.GlinkPkg.all;

 --! @see entity
  --! @ingroup protocols_glink_gtp7
 entity GLinkGtp7FixedLat is
    generic (
       -- GLink Settings
       FLAGSEL_G             : boolean    := false;
       SYNTH_TX_G            : boolean    := true;
       SYNTH_RX_G            : boolean    := true;
       -- Simulation Generics
       TPD_G                 : time       := 1 ns;
       SIM_GTRESET_SPEEDUP_G : string     := "FALSE";
       SIM_VERSION_G         : string     := "4.0";
       SIMULATION_G          : boolean    := false;
       -- MGT Settings
       RXOUT_DIV_G           : integer    := 2;
       TXOUT_DIV_G           : integer    := 2;
       RX_CLK25_DIV_G        : integer    := 5;                         -- Set by wizard
       TX_CLK25_DIV_G        : integer    := 5;                         -- Set by wizard
       PMA_RSV_G             : bit_vector := x"00000333";               -- Set by wizard
       RX_OS_CFG_G           : bit_vector := "0001111110000";           -- Set by wizard
       RXCDR_CFG_G           : bit_vector := x"0000107FE206001041010";  -- Set by wizard
       RXLPM_INCM_CFG_G      : bit        := '1';                       -- Set by wizard
       RXLPM_IPCM_CFG_G      : bit        := '0';                       -- Set by wizard
       -- Configure PLL sources
       TX_PLL_G              : string     := "PLL0";
       RX_PLL_G              : string     := "PLL1");
    port (
       -- G-Link TX Interface (gLinkTxClk Domain)
       gLinkTx          : in  GLinkTxType;
       txReady          : out sl;
       gLinkTxClk       : in  sl;
       gLinkTxClkEn     : in  sl := '1';
       -- G-Link TX Interface (gLinkClk Domain)
       gLinkRx          : out GLinkRxType;
       rxReady          : out sl;
       gLinkRxClk       : in  sl;
       gLinkRxClkEn     : in  sl := '1';
       -- MGT Clocking
       gLinkTxRefClk    : in  sl;                                       -- G-Link TX clock reference
       stableClk        : in  sl;
       gtQPllRefClk     : in  slv(1 downto 0);
       gtQPllClk        : in  slv(1 downto 0);
       gtQPllLock       : in  slv(1 downto 0);
       gtQPllRefClkLost : in  slv(1 downto 0);
       gtQPllReset      : out slv(1 downto 0);
       -- MGT loopback control
       loopback         : in  slv(2 downto 0);
       -- MGT Serial IO
       gtTxP            : out sl;
       gtTxN            : out sl;
       gtRxP            : in  sl;
       gtRxN            : in  sl);

 end GLinkGtp7FixedLat;

 architecture rtl of GLinkGtp7FixedLat is

    constant FIXED_ALIGN_COMMA_0_C : slv(19 downto 0) := bitReverse((GLINK_VALID_IDLE_WORDS_C(0) & GLINK_CONTROL_WORD_C));  -- FF0
    constant FIXED_ALIGN_COMMA_1_C : slv(19 downto 0) := bitReverse((GLINK_VALID_IDLE_WORDS_C(1) & GLINK_CONTROL_WORD_C));  -- FF1A
    constant FIXED_ALIGN_COMMA_2_C : slv(19 downto 0) := bitReverse((GLINK_VALID_IDLE_WORDS_C(2) & GLINK_CONTROL_WORD_C));  -- FF1B

    signal txFifoValid,
       rxFifoValid,
       rxRecClk,
       rxClk,
       rxRst,
       txClk,
       gtTxRstDone,
       gtRxRstDone,
       gtTxRst,
       gtRxRst,
       dataValid : sl := '0';
    signal txFifoDout,
       gtTxData,
       gtRxData,
       gtTxDataReversed,
       gtRxDataReversed : slv(19 downto 0) := (others => '0');
    signal rxFifoDout  : slv(23 downto 0);
    signal gLinkTxSync : GLinkTxType;
    signal gLinkRxSync : GLinkRxType;

 begin

    SYNTH_TX : if (SYNTH_TX_G = true) generate

       txClk <= gLinkTxRefClk;

       Synchronizer_0 : entity work.Synchronizer
          generic map (
             TPD_G => TPD_G)
          port map (
             clk     => gLinkTxClk,
             dataIn  => gtTxRstDone,
             dataOut => txReady);

       SyncFifo_TX : entity work.SynchronizerFifo
          generic map (
             TPD_G        => TPD_G,
             INIT_G       => toSlv(GLINK_TX_UNUSED_C),
             DATA_WIDTH_G => 20)
          port map (
             --Write Ports (wr_clk domain)
             wr_clk => gLinkTxClk,
             wr_en  => gLinkTxClkEn,
             din    => toSlv(gLinkTx),
             --Read Ports (rd_clk domain)
             rd_clk => txClk,
             valid  => txFifoValid,
             dout   => txFifoDout);

       gLinkTxSync <= toGLinkTx(txFifoDout) when(txFifoValid = '1') else GLINK_TX_UNUSED_C;

       gtTxRst <= not(gtTxRstDone) or gLinkTxSync.linkRst;

       GLinkEncoder_Inst : entity work.GLinkEncoder
          generic map (
             TPD_G          => TPD_G,
             FLAGSEL_G      => FLAGSEL_G,
             RST_POLARITY_G => '1')
          port map (
             clk         => txClk,
             rst         => gtTxRst,
             gLinkTx     => gLinkTxSync,
             encodedData => gtTxData);

    end generate;

    DISABLE_SYNTH_TX : if (SYNTH_TX_G = false) generate

       txClk       <= '0';
       txReady     <= '1';
       gLinkTxSync <= GLINK_TX_UNUSED_C;
       gtTxRst     <= '0';
       gtTxData    <= (GLINK_IDLE_WORD_FF0_C & GLINK_CONTROL_WORD_C);

    end generate;

    SYNTH_RX : if (SYNTH_RX_G = true) generate

       rxClk <= rxRecClk;

       Synchronizer_1 : entity work.Synchronizer
          generic map (
             TPD_G => TPD_G)
          port map (
             clk     => gLinkRxClk,
             dataIn  => gtRxRstDone,
             dataOut => rxReady);

       SyncFifo_RX : entity work.SynchronizerFifo
          generic map (
             TPD_G        => TPD_G,
             INIT_G       => toSlv(GLINK_RX_INIT_C),
             DATA_WIDTH_G => 24)
          port map (
             -- Asynchronous Reset
             rst    => gtRxRst,
             --Write Ports (wr_clk domain)
             wr_clk => rxClk,
             wr_en  => gtRxRstDone,
             din    => toSlv(gLinkRxSync),
             --Read Ports (rd_clk domain)
             rd_clk => gLinkRxClk,
             rd_en  => gLinkRxClkEn,
             valid  => rxFifoValid,
             dout   => rxFifoDout);

       gLinkRx <= toGLinkRx(rxFifoDout);

       rxRst   <= '0';
       gtRxRst <= not(gtRxRstDone) or rxRst;

       GLinkDecoder_Inst : entity work.GLinkDecoder
          generic map (
             TPD_G          => TPD_G,
             FLAGSEL_G      => FLAGSEL_G,
             RST_POLARITY_G => '1')
          port map (
             clk           => rxClk,
             rst           => gtRxRst,
             gtRxData      => gtRxData,
             rxReady       => gtRxRstDone,
             txReady       => gtTxRstDone,
             gLinkRx       => gLinkRxSync,
             decoderErrorL => dataValid);

    end generate;

    DISABLE_SYNTH_RX : if (SYNTH_RX_G = false) generate

       rxClk     <= '0';
       rxReady   <= '1';
       gLinkRx   <= GLINK_RX_INIT_C;
       rxRst     <= '0';
       gtRxRst   <= '0';
       dataValid <= '1';

    end generate;

    gtTxDataReversed <= bitReverse(gtTxData);
    gtRxData         <= bitReverse(gtRxDataReversed);

    -- GTP 7 Core in Fixed Latency mode
    Gtp7Core_Inst : entity work.Gtp7Core
       generic map (
          TPD_G                 => TPD_G,
          SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_G,
          SIM_VERSION_G         => SIM_VERSION_G,
          SIMULATION_G          => SIMULATION_G,
          STABLE_CLOCK_PERIOD_G => 4.0E-9,
          RXOUT_DIV_G           => RXOUT_DIV_G,
          TXOUT_DIV_G           => TXOUT_DIV_G,
          RX_CLK25_DIV_G        => RX_CLK25_DIV_G,
          TX_CLK25_DIV_G        => TX_CLK25_DIV_G,
          PMA_RSV_G             => PMA_RSV_G,
          RX_OS_CFG_G           => RX_OS_CFG_G,
          RXCDR_CFG_G           => RXCDR_CFG_G,
          RXLPM_INCM_CFG_G      => RXLPM_INCM_CFG_G,
          RXLPM_IPCM_CFG_G      => RXLPM_IPCM_CFG_G,
          TX_PLL_G              => TX_PLL_G,
          RX_PLL_G              => RX_PLL_G,
          TX_EXT_DATA_WIDTH_G   => 20,
          TX_INT_DATA_WIDTH_G   => 20,
          TX_8B10B_EN_G         => false,
          RX_EXT_DATA_WIDTH_G   => 20,
          RX_INT_DATA_WIDTH_G   => 20,
          RX_8B10B_EN_G         => false,
          TX_BUF_EN_G           => false,
          TX_OUTCLK_SRC_G       => "PLLREFCLK",
          TX_DLY_BYPASS_G       => '0',
          TX_PHASE_ALIGN_G      => "MANUAL",
          RX_BUF_EN_G           => false,
          RX_OUTCLK_SRC_G       => "OUTCLKPMA",
          RX_USRCLK_SRC_G       => "RXOUTCLK",
          RX_DLY_BYPASS_G       => '1',
          RX_DDIEN_G            => '0',
          RX_ALIGN_MODE_G       => "FIXED_LAT",
          RXSLIDE_MODE_G        => "PMA",
          FIXED_COMMA_EN_G      => "0111",
          FIXED_ALIGN_COMMA_0_G => FIXED_ALIGN_COMMA_0_C,
          FIXED_ALIGN_COMMA_1_G => FIXED_ALIGN_COMMA_1_C,
          FIXED_ALIGN_COMMA_2_G => FIXED_ALIGN_COMMA_2_C,
          FIXED_ALIGN_COMMA_3_G => "XXXXXXXXXXXXXXXXXXXX")
       port map (
          stableClkIn      => stableClk,
          qPllRefClkIn     => gtQPllRefClk,
          qPllClkIn        => gtQPllClk,
          qPllLockIn       => gtQPllLock,
          qPllRefClkLostIn => gtQPllRefClkLost,
          qPllResetOut     => gtQPllReset,
          gtTxP            => gtTxP,
          gtTxN            => gtTxN,
          gtRxP            => gtRxP,
          gtRxN            => gtRxN,
          gtRxRefClkBufg   => gLinkTxRefClk,
          rxOutClkOut      => rxRecClk,
          rxUsrClkIn       => rxClk,
          rxUsrClk2In      => rxClk,
          rxUserRdyOut     => open,
          rxMmcmResetOut   => open,
          rxMmcmLockedIn   => '1',
          rxUserResetIn    => rxRst,
          rxResetDoneOut   => gtRxRstDone,
          rxDataValidIn    => dataValid,
          rxSlideIn        => '0',              -- Slide is controlled internally
          rxDataOut        => gtRxDataReversed,
          rxCharIsKOut     => open,             -- Not using gt rx 8b10b
          rxDecErrOut      => open,             -- Not using gt rx 8b10b
          rxDispErrOut     => open,             -- Not using gt rx 8b10b
          rxPolarityIn     => '0',
          rxBufStatusOut   => open,
          txOutClkOut      => open,
          txUsrClkIn       => txClk,
          txUsrClk2In      => txClk,
          txUserRdyOut     => open,             -- Not sure what to do with this
          txMmcmResetOut   => open,             -- No Tx MMCM in Fixed Latency mode
          txMmcmLockedIn   => '1',
          txUserResetIn    => gLinkTxSync.linkRst,
          txResetDoneOut   => gtTxRstDone,
          txDataIn         => gtTxDataReversed,
          txCharIsKIn      => (others => '0'),  -- Not using gt rx 8b10b
          txBufStatusOut   => open,
          loopbackIn       => loopback);
 end rtl;
Gtp7Core.rxUsrClkIn
in rxUsrClkInsl
Definition: Gtp7Core.vhd:167

Gtp7Core.TPD_G
TPD_Gtime  :=  1 ns
Definition: Gtp7Core.vhd:31

Gtp7Core.txUserResetIn
in txUserResetInsl
Definition: Gtp7Core.vhd:203

Gtp7Core.SIM_VERSION_G
SIM_VERSION_Gstring  :=   "1.0"
Definition: Gtp7Core.vhd:35

GLinkGtp7FixedLat
Definition: GLinkGtp7FixedLat.vhd:27

Gtp7Core.TX_EXT_DATA_WIDTH_G
TX_EXT_DATA_WIDTH_Ginteger  := 16
Definition: Gtp7Core.vhd:58

GLinkEncoder.encodedData
out encodedDataslv( 19 downto  0)
Definition: GLinkEncoder.vhd:38

Gtp7Core.RX_EXT_DATA_WIDTH_G
RX_EXT_DATA_WIDTH_Ginteger  := 16
Definition: Gtp7Core.vhd:62

Gtp7Core.TX_INT_DATA_WIDTH_G
TX_INT_DATA_WIDTH_Ginteger  := 20
Definition: Gtp7Core.vhd:59

Gtp7Core.RX_DLY_BYPASS_G
RX_DLY_BYPASS_Gsl  := '1'
Definition: Gtp7Core.vhd:76

Gtp7Core.qPllLockIn
in qPllLockInslv( 1 downto  0)
Definition: Gtp7Core.vhd:153

Gtp7Core.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0001111110000"
Definition: Gtp7Core.vhd:48

Gtp7Core.FIXED_ALIGN_COMMA_0_G
FIXED_ALIGN_COMMA_0_Gslv  :=   "----------0101111100"
Definition: Gtp7Core.vhd:96

GLinkGtp7FixedLat.RXOUT_DIV_G
RXOUT_DIV_Ginteger  := 2
Definition: GLinkGtp7FixedLat.vhd:39

Gtp7Core.RXOUT_DIV_G
RXOUT_DIV_Ginteger  := 2
Definition: Gtp7Core.vhd:43

Gtp7Core.qPllRefClkLostIn
in qPllRefClkLostInslv( 1 downto  0)
Definition: Gtp7Core.vhd:154

StdRtlPkg.sl
std_logic   sl
Definition: StdRtlPkg.vhd:28

SynchronizerFifo.wr_en
in wr_ensl  := '1'
Definition: SynchronizerFifo.vhd:44

GLinkEncoder
Definition: GLinkEncoder.vhd:27

SynchronizerFifo.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: SynchronizerFifo.vhd:45

Gtp7Core.RX_DDIEN_G
RX_DDIEN_Gsl  := '0'
Definition: Gtp7Core.vhd:77

Gtp7Core.stableClkIn
in stableClkInsl
Definition: Gtp7Core.vhd:149

GLinkGtp7FixedLat.PMA_RSV_G
PMA_RSV_Gbit_vector  := x"00000333"
Definition: GLinkGtp7FixedLat.vhd:43

GLinkDecoder.gtRxData
in gtRxDataslv( 19 downto  0)
Definition: GLinkDecoder.vhd:38

Gtp7Core.rxCharIsKOut
out rxCharIsKOutslv((   RX_EXT_DATA_WIDTH_G/ 8)- 1 downto  0)
Definition: Gtp7Core.vhd:183

Gtp7Core.RX_PLL_G
RX_PLL_Gstring  :=   "PLL1"
Definition: Gtp7Core.vhd:55

GLinkGtp7FixedLat.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0001111110000"
Definition: GLinkGtp7FixedLat.vhd:44

GLinkGtp7FixedLat.gtTxN
out gtTxNsl
Definition: GLinkGtp7FixedLat.vhd:74

GLinkGtp7FixedLat.txReady
out txReadysl
Definition: GLinkGtp7FixedLat.vhd:54

GLinkGtp7FixedLat.gLinkRxClkEn
in gLinkRxClkEnsl  := '1'
Definition: GLinkGtp7FixedLat.vhd:61

GLinkDecoder.gLinkRx
out gLinkRxGLinkRxType
Definition: GLinkDecoder.vhd:41

GLinkGtp7FixedLat.gLinkTxClk
in gLinkTxClksl
Definition: GLinkGtp7FixedLat.vhd:55

Gtp7Core.TX_PHASE_ALIGN_G
TX_PHASE_ALIGN_Gstring  :=   "AUTO"
Definition: Gtp7Core.vhd:70

GLinkGtp7FixedLat.TX_PLL_G
TX_PLL_Gstring  :=   "PLL0"
Definition: GLinkGtp7FixedLat.vhd:49

GLinkGtp7FixedLat.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger  := 5
Definition: GLinkGtp7FixedLat.vhd:41

Gtp7Core.txCharIsKIn
in txCharIsKInslv((   TX_EXT_DATA_WIDTH_G/ 8)- 1 downto  0)
Definition: Gtp7Core.vhd:208

Gtp7Core.txUserRdyOut
out txUserRdyOutsl
Definition: Gtp7Core.vhd:198

GLinkGtp7FixedLat.gLinkRx
out gLinkRxGLinkRxType
Definition: GLinkGtp7FixedLat.vhd:58

Gtp7Core.txBufStatusOut
out txBufStatusOutslv( 1 downto  0)
Definition: Gtp7Core.vhd:209

Gtp7Core.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger  := 5
Definition: Gtp7Core.vhd:46

GLinkGtp7FixedLat.gtQPllReset
out gtQPllResetslv( 1 downto  0)
Definition: GLinkGtp7FixedLat.vhd:69

Gtp7Core.rxUserResetIn
in rxUserResetInsl
Definition: Gtp7Core.vhd:174

Gtp7Core.gtTxN
out gtTxNsl
Definition: Gtp7Core.vhd:161

GLinkDecoder.TPD_G
TPD_Gtime  :=  1 ns
Definition: GLinkDecoder.vhd:30

GLinkGtp7FixedLat.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger  := 5
Definition: GLinkGtp7FixedLat.vhd:42

GLinkGtp7FixedLat.SYNTH_RX_G
SYNTH_RX_Gboolean  :=   true
Definition: GLinkGtp7FixedLat.vhd:32

Gtp7Core.qPllResetOut
out qPllResetOutslv( 1 downto  0)
Definition: Gtp7Core.vhd:155

GLinkGtp7FixedLat.stableClk
in stableClksl
Definition: GLinkGtp7FixedLat.vhd:64

Gtp7Core.FIXED_ALIGN_COMMA_1_G
FIXED_ALIGN_COMMA_1_Gslv  :=   "----------1010000011"
Definition: Gtp7Core.vhd:97

GLinkEncoder.clk
in clksl
Definition: GLinkEncoder.vhd:35

GLinkGtp7FixedLat.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0000107FE206001041010"
Definition: GLinkGtp7FixedLat.vhd:45

Gtp7Core.txMmcmLockedIn
in txMmcmLockedInsl  := '1'
Definition: Gtp7Core.vhd:200

GLinkGtp7FixedLat.FLAGSEL_G
FLAGSEL_Gboolean  :=   false
Definition: GLinkGtp7FixedLat.vhd:30

Synchronizer.dataOut
out dataOutsl
Definition: Synchronizer.vhd:39

SynchronizerFifo.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: SynchronizerFifo.vhd:50

Gtp7Core.rxBufStatusOut
out rxBufStatusOutslv( 2 downto  0)
Definition: Gtp7Core.vhd:187

GLinkGtp7FixedLat.RXLPM_INCM_CFG_G
RXLPM_INCM_CFG_Gbit  := '1'
Definition: GLinkGtp7FixedLat.vhd:46

Gtp7Core.SIM_GTRESET_SPEEDUP_G
SIM_GTRESET_SPEEDUP_Gstring  :=   "FALSE"
Definition: Gtp7Core.vhd:34

Gtp7Core.rxSlideIn
in rxSlideInsl  := '0'
Definition: Gtp7Core.vhd:179

Gtp7Core.rxDataValidIn
in rxDataValidInsl  := '1'
Definition: Gtp7Core.vhd:178

SynchronizerFifo.valid
out validsl
Definition: SynchronizerFifo.vhd:49

SynchronizerFifo.rd_en
in rd_ensl  := '1'
Definition: SynchronizerFifo.vhd:48

GLinkGtp7FixedLat.gLinkTx
in gLinkTxGLinkTxType
Definition: GLinkGtp7FixedLat.vhd:53

SynchronizerFifo.INIT_G
INIT_Gslv  :=   "0"
Definition: SynchronizerFifo.vhd:38

GLinkEncoder.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: GLinkEncoder.vhd:31

GLinkGtp7FixedLat.rxReady
out rxReadysl
Definition: GLinkGtp7FixedLat.vhd:59

GLinkEncoder.gLinkTx
in gLinkTxGLinkTxType
Definition: GLinkEncoder.vhd:37

Gtp7Core.rxDataOut
out rxDataOutslv(   RX_EXT_DATA_WIDTH_G- 1 downto  0)
Definition: Gtp7Core.vhd:182

SynchronizerFifo
Definition: SynchronizerFifo.vhd:27

Gtp7Core.TX_BUF_EN_G
TX_BUF_EN_Gboolean  :=   true
Definition: Gtp7Core.vhd:67

Gtp7Core.FIXED_COMMA_EN_G
FIXED_COMMA_EN_Gslv( 3 downto  0)  :=   "0011"
Definition: Gtp7Core.vhd:95

Gtp7Core.TX_PLL_G
TX_PLL_Gstring  :=   "PLL0"
Definition: Gtp7Core.vhd:54

GLinkGtp7FixedLat.SYNTH_TX_G
SYNTH_TX_Gboolean  :=   true
Definition: GLinkGtp7FixedLat.vhd:31

GLinkGtp7FixedLat.gtQPllLock
in gtQPllLockslv( 1 downto  0)
Definition: GLinkGtp7FixedLat.vhd:67

Gtp7Core.txDataIn
in txDataInslv(   TX_EXT_DATA_WIDTH_G- 1 downto  0)
Definition: Gtp7Core.vhd:207

Gtp7Core.rxUserRdyOut
out rxUserRdyOutsl
Definition: Gtp7Core.vhd:169

Gtp7Core.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0000107FE206001041010"
Definition: Gtp7Core.vhd:49

Gtp7Core.rxMmcmLockedIn
in rxMmcmLockedInsl  := '1'
Definition: Gtp7Core.vhd:171

GLinkGtp7FixedLat.gLinkTxRefClk
in gLinkTxRefClksl
Definition: GLinkGtp7FixedLat.vhd:63

Gtp7Core.qPllRefClkIn
in qPllRefClkInslv( 1 downto  0)
Definition: Gtp7Core.vhd:151

GLinkDecoder.rst
in rstsl
Definition: GLinkDecoder.vhd:37

GLinkGtp7FixedLat.loopback
in loopbackslv( 2 downto  0)
Definition: GLinkGtp7FixedLat.vhd:71

Gtp7Core.RX_OUTCLK_SRC_G
RX_OUTCLK_SRC_Gstring  :=   "PLLREFCLK"
Definition: Gtp7Core.vhd:74

Gtp7Core.gtRxRefClkBufg
in gtRxRefClkBufgsl  := '0'
Definition: Gtp7Core.vhd:156

GLinkDecoder.rxReady
in rxReadysl
Definition: GLinkDecoder.vhd:39

Gtp7Core.RX_ALIGN_MODE_G
RX_ALIGN_MODE_Gstring  :=   "GT"
Definition: Gtp7Core.vhd:81

GLinkGtp7FixedLat.gtQPllClk
in gtQPllClkslv( 1 downto  0)
Definition: GLinkGtp7FixedLat.vhd:66

GLinkGtp7FixedLat.gtQPllRefClk
in gtQPllRefClkslv( 1 downto  0)
Definition: GLinkGtp7FixedLat.vhd:65

Synchronizer.TPD_G
TPD_Gtime  :=  1 ns
Definition: Synchronizer.vhd:28

Gtp7Core.gtRxP
in gtRxPsl
Definition: Gtp7Core.vhd:162

GLinkGtp7FixedLat.gtTxP
out gtTxPsl
Definition: GLinkGtp7FixedLat.vhd:73

GLinkEncoder.TPD_G
TPD_Gtime  :=  1 ns
Definition: GLinkEncoder.vhd:29

SynchronizerFifo.rst
in rstsl  := '0'
Definition: SynchronizerFifo.vhd:41

Gtp7Core.RXSLIDE_MODE_G
RXSLIDE_MODE_Gstring  :=   "PCS"
Definition: Gtp7Core.vhd:92

Gtp7Core.gtRxN
in gtRxNsl
Definition: Gtp7Core.vhd:163

Gtp7Core.txUsrClkIn
in txUsrClkInsl
Definition: Gtp7Core.vhd:196

Synchronizer.clk
in clksl
Definition: Synchronizer.vhd:36

GLinkDecoder.decoderErrorL
out decoderErrorLsl
Definition: GLinkDecoder.vhd:43

GLinkGtp7FixedLat.gLinkTxClkEn
in gLinkTxClkEnsl  := '1'
Definition: GLinkGtp7FixedLat.vhd:56

GLinkDecoder.FLAGSEL_G
FLAGSEL_Gboolean  :=   false
Definition: GLinkDecoder.vhd:33

Gtp7Core.txMmcmResetOut
out txMmcmResetOutsl
Definition: Gtp7Core.vhd:199

Gtp7Core.qPllClkIn
in qPllClkInslv( 1 downto  0)
Definition: Gtp7Core.vhd:152

Gtp7Core.rxPolarityIn
in rxPolarityInsl  := '0'
Definition: Gtp7Core.vhd:186

Gtp7Core.rxUsrClk2In
in rxUsrClk2Insl
Definition: Gtp7Core.vhd:168

Gtp7Core.RXLPM_INCM_CFG_G
RXLPM_INCM_CFG_Gbit  := '1'
Definition: Gtp7Core.vhd:50

SynchronizerFifo.TPD_G
TPD_Gtime  :=  1 ns
Definition: SynchronizerFifo.vhd:29

GLinkEncoder.rst
in rstsl
Definition: GLinkEncoder.vhd:36

Gtp7Core.rxDecErrOut
out rxDecErrOutslv((   RX_EXT_DATA_WIDTH_G/ 8)- 1 downto  0)
Definition: Gtp7Core.vhd:184

Gtp7Core.rxDispErrOut
out rxDispErrOutslv((   RX_EXT_DATA_WIDTH_G/ 8)- 1 downto  0)
Definition: Gtp7Core.vhd:185

Gtp7Core.txOutClkOut
out txOutClkOutsl
Definition: Gtp7Core.vhd:195

Gtp7Core.gtTxP
out gtTxPsl
Definition: Gtp7Core.vhd:160

Gtp7Core.FIXED_ALIGN_COMMA_3_G
FIXED_ALIGN_COMMA_3_Gslv  :=   "XXXXXXXXXXXXXXXXXXXX"
Definition: Gtp7Core.vhd:99

GLinkGtp7FixedLat.gtQPllRefClkLost
in gtQPllRefClkLostslv( 1 downto  0)
Definition: GLinkGtp7FixedLat.vhd:68

GLinkEncoder.FLAGSEL_G
FLAGSEL_Gboolean  :=   false
Definition: GLinkEncoder.vhd:32

GLinkGtp7FixedLat.RX_PLL_G
RX_PLL_Gstring  :=   "PLL1"
Definition: GLinkGtp7FixedLat.vhd:50

Gtp7Core.loopbackIn
in loopbackInslv( 2 downto  0)  :=   "000"
Definition: Gtp7Core.vhd:214

Gtp7Core.RX_USRCLK_SRC_G
RX_USRCLK_SRC_Gstring  :=   "RXOUTCLK"
Definition: Gtp7Core.vhd:75

Gtp7Core.TX_DLY_BYPASS_G
TX_DLY_BYPASS_Gsl  := '1'
Definition: Gtp7Core.vhd:69

SynchronizerFifo.wr_clk
in wr_clksl
Definition: SynchronizerFifo.vhd:43

Gtp7Core.SIMULATION_G
SIMULATION_Gboolean  :=   false
Definition: Gtp7Core.vhd:37

Gtp7Core.TX_OUTCLK_SRC_G
TX_OUTCLK_SRC_Gstring  :=   "PLLREFCLK"
Definition: Gtp7Core.vhd:68

Gtp7Core.txUsrClk2In
in txUsrClk2Insl
Definition: Gtp7Core.vhd:197

GLinkGtp7FixedLat.SIMULATION_G
SIMULATION_Gboolean  :=   false
Definition: GLinkGtp7FixedLat.vhd:37

GLinkDecoder.txReady
in txReadysl
Definition: GLinkDecoder.vhd:40

GLinkGtp7FixedLat.gtRxN
in gtRxNsl
Definition: GLinkGtp7FixedLat.vhd:76

Gtp7Core.rxMmcmResetOut
out rxMmcmResetOutsl
Definition: Gtp7Core.vhd:170

GLinkGtp7FixedLat.SIM_GTRESET_SPEEDUP_G
SIM_GTRESET_SPEEDUP_Gstring  :=   "FALSE"
Definition: GLinkGtp7FixedLat.vhd:35

GLinkDecoder.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: GLinkDecoder.vhd:32

Gtp7Core.FIXED_ALIGN_COMMA_2_G
FIXED_ALIGN_COMMA_2_Gslv  :=   "XXXXXXXXXXXXXXXXXXXX"
Definition: Gtp7Core.vhd:98

Gtp7Core.RXLPM_IPCM_CFG_G
RXLPM_IPCM_CFG_Gbit  := '0'
Definition: Gtp7Core.vhd:51

GLinkGtp7FixedLat.gLinkRxClk
in gLinkRxClksl
Definition: GLinkGtp7FixedLat.vhd:60

StdRtlPkg
Definition: StdRtlPkg.vhd:23

GLinkGtp7FixedLat.RXLPM_IPCM_CFG_G
RXLPM_IPCM_CFG_Gbit  := '0'
Definition: GLinkGtp7FixedLat.vhd:47

Gtp7Core.RX_BUF_EN_G
RX_BUF_EN_Gboolean  :=   true
Definition: Gtp7Core.vhd:73

Gtp7Core.STABLE_CLOCK_PERIOD_G
STABLE_CLOCK_PERIOD_Greal  := 4.0E-9
Definition: Gtp7Core.vhd:39

Gtp7Core.rxResetDoneOut
out rxResetDoneOutsl
Definition: Gtp7Core.vhd:175

GLinkGtp7FixedLat.TPD_G
TPD_Gtime  :=  1 ns
Definition: GLinkGtp7FixedLat.vhd:34

Gtp7Core.rxOutClkOut
out rxOutClkOutsl
Definition: Gtp7Core.vhd:166

GLinkTxToRx.ieee
_library_ ieeeieee
Definition: GLinkTxToRx.vhd:18

Gtp7Core.PMA_RSV_G
PMA_RSV_Gbit_vector  := x"00000333"
Definition: Gtp7Core.vhd:47

Gtp7Core
Definition: Gtp7Core.vhd:28

GLinkGtp7FixedLat.TXOUT_DIV_G
TXOUT_DIV_Ginteger  := 2
Definition: GLinkGtp7FixedLat.vhd:40

SynchronizerFifo.rd_clk
in rd_clksl
Definition: SynchronizerFifo.vhd:47

GLinkGtp7FixedLat.gtRxP
in gtRxPsl
Definition: GLinkGtp7FixedLat.vhd:75

GLinkGtp7FixedLat.SIM_VERSION_G
SIM_VERSION_Gstring  :=   "4.0"
Definition: GLinkGtp7FixedLat.vhd:36

Gtp7Core.TX_8B10B_EN_G
TX_8B10B_EN_Gboolean  :=   true
Definition: Gtp7Core.vhd:60

Gtp7Core.RX_INT_DATA_WIDTH_G
RX_INT_DATA_WIDTH_Ginteger  := 20
Definition: Gtp7Core.vhd:63

Synchronizer
Definition: Synchronizer.vhd:26

GLinkDecoder
Definition: GLinkDecoder.vhd:28

GLinkDecoder.clk
in clksl
Definition: GLinkDecoder.vhd:36

Gtp7Core.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger  := 5
Definition: Gtp7Core.vhd:45

Gtp7Core.TXOUT_DIV_G
TXOUT_DIV_Ginteger  := 2
Definition: Gtp7Core.vhd:44

SynchronizerFifo.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to ( 2** 24):= 16
Definition: SynchronizerFifo.vhd:36

Gtp7Core.txResetDoneOut
out txResetDoneOutsl
Definition: Gtp7Core.vhd:204

StdRtlPkg.slv
std_logic_vector   slv
Definition: StdRtlPkg.vhd:29

Gtp7Core.RX_8B10B_EN_G
RX_8B10B_EN_Gboolean  :=   true
Definition: Gtp7Core.vhd:64

Synchronizer.dataIn
in dataInsl
Definition: Synchronizer.vhd:38