SURF  1.0
Generics | Ports | Libraries | Use Clauses
SynchronizerFifo Entity Reference
base » sync
+ Inheritance diagram for SynchronizerFifo:
+ Collaboration diagram for SynchronizerFifo:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
COMMON_CLK_G  boolean := false
BRAM_EN_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
SYNC_STAGES_G  integer range 3 to ( 2 ** 24 ) := 3
PIPE_STAGES_G  natural range 0 to 16 := 0
DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 16
ADDR_WIDTH_G  integer range 2 to 48 := 4
INIT_G  slv := " 0 "

Ports

rst   in sl := ' 0 '
wr_clk   in sl
wr_en   in sl := ' 1 '
din   in slv ( DATA_WIDTH_G - 1 downto 0 )
rd_clk   in sl
rd_en   in sl := ' 1 '
valid   out sl
dout   out slv ( DATA_WIDTH_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 27 of file SynchronizerFifo.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file SynchronizerFifo.vhd.

◆ COMMON_CLK_G

COMMON_CLK_G boolean := false
Generic

Definition at line 30 of file SynchronizerFifo.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := false
Generic

Definition at line 31 of file SynchronizerFifo.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 32 of file SynchronizerFifo.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 33 of file SynchronizerFifo.vhd.

◆ SYNC_STAGES_G

SYNC_STAGES_G integer range 3 to ( 2 ** 24 ) := 3
Generic

Definition at line 34 of file SynchronizerFifo.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 35 of file SynchronizerFifo.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 16
Generic

Definition at line 36 of file SynchronizerFifo.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 2 to 48 := 4
Generic

Definition at line 37 of file SynchronizerFifo.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 38 of file SynchronizerFifo.vhd.

◆ rst

rst in sl := ' 0 '
Port

Definition at line 41 of file SynchronizerFifo.vhd.

◆ wr_clk

wr_clk in sl
Port

Definition at line 43 of file SynchronizerFifo.vhd.

◆ wr_en

wr_en in sl := ' 1 '
Port

Definition at line 44 of file SynchronizerFifo.vhd.

◆ din

din in slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 45 of file SynchronizerFifo.vhd.

◆ rd_clk

rd_clk in sl
Port

Definition at line 47 of file SynchronizerFifo.vhd.

◆ rd_en

rd_en in sl := ' 1 '
Port

Definition at line 48 of file SynchronizerFifo.vhd.

◆ valid

valid out sl
Port

Definition at line 49 of file SynchronizerFifo.vhd.

◆ dout

dout out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 50 of file SynchronizerFifo.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file SynchronizerFifo.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file SynchronizerFifo.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file SynchronizerFifo.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file SynchronizerFifo.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file SynchronizerFifo.vhd.

The documentation for this class was generated from the following file: