SURF  1.0
AxiAds42lb69Pll.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : AxiAds42lb69Pll.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-03-20
5 -- Last update: 2016-09-20
6 -------------------------------------------------------------------------------
7 -- Description: PLL Module
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 library unisim;
24 use unisim.vcomponents.all;
25 
26 --! @see entity
27  --! @ingroup devices_Ti_ads42lb69
28 entity AxiAds42lb69Pll is
29  generic (
30  TPD_G : time := 1 ns;
31  USE_PLL_G : boolean := true;
32  ADC_CLK_FREQ_G : real := 250.0E+6;
33  XIL_DEVICE_G : string := "7SERIES");
34  port (
35  -- ADC Clocking ports
36  adcClkP : out sl;
37  adcClkN : out sl;
38  adcSyncP : out sl;
39  adcSyncN : out sl;
40  adcClkFbP : in sl;
41  adcClkFbN : in sl;
42  -- ADC Reference Signals
43  adcSync : in sl;
44  adcClk : in sl;
45  adcRst : in sl;
46  adcClock : out sl);
47 end AxiAds42lb69Pll;
48 
49 architecture mapping of AxiAds42lb69Pll is
50 
51  constant ADC_CLK_PERIOD_NS_C : real := 1.0E+9 / ADC_CLK_FREQ_G;
52 
53  signal clkFeedBack : sl;
54  signal clkFeedBackIn : sl;
55  signal clkFeedBackOut : sl;
56 
57  signal sync : sl;
58  signal syncOut : sl;
59  signal adcInClk : sl;
60 
61 begin
62 
63  GEN_PLL : if (USE_PLL_G = true and XIL_DEVICE_G = "7SERIES") generate
64 
65  IBUFGDS_0 : IBUFGDS
66  port map (
67  I => adcClkFbP,
68  IB => adcClkFbN,
69  O => clkFeedBackIn);
70 
71  MMCME2_ADV_0 : MMCME2_ADV
72  generic map(
73  BANDWIDTH => "LOW",
74  CLKOUT4_CASCADE => false,
75  COMPENSATION => "ZHOLD",
76  STARTUP_WAIT => false,
77  DIVCLK_DIVIDE => 1,
78  CLKFBOUT_MULT_F => ADC_CLK_PERIOD_NS_C,
79  CLKFBOUT_PHASE => 0.000,
80  CLKFBOUT_USE_FINE_PS => false,
81  CLKIN1_PERIOD => ADC_CLK_PERIOD_NS_C,
82  REF_JITTER1 => 0.100)
83  port map (
84  -- Output clocks
85  CLKFBOUT => clkFeedBack,
86  CLKFBOUTB => open,
87  CLKOUT0 => open,
88  CLKOUT0B => open,
89  CLKOUT1 => open,
90  CLKOUT1B => open,
91  CLKOUT2 => open,
92  CLKOUT2B => open,
93  CLKOUT3 => open,
94  CLKOUT3B => open,
95  CLKOUT4 => open,
96  CLKOUT5 => open,
97  CLKOUT6 => open,
98  -- Input clock control
99  CLKFBIN => clkFeedBackIn,
100  CLKIN1 => adcClk,
101  CLKIN2 => '0',
102  -- Tied to always select the primary input clock
103  CLKINSEL => '1',
104  -- Ports for dynamic reconfiguration
105  DADDR => (others => '0'),
106  DCLK => '0',
107  DEN => '0',
108  DI => (others => '0'),
109  DO => open,
110  DRDY => open,
111  DWE => '0',
112  -- Ports for dynamic phase shift
113  PSCLK => '0',
114  PSEN => '0',
115  PSINCDEC => '0',
116  PSDONE => open,
117  -- Other control and status signals
118  LOCKED => open,
119  CLKINSTOPPED => open,
120  CLKFBSTOPPED => open,
121  PWRDWN => '0',
122  RST => adcRst);
123 
124  BUFH_0 : BUFH
125  port map (
126  I => clkFeedBack,
127  O => clkFeedBackOut);
128 
129  ClkOutBufDiff_0 : entity work.ClkOutBufDiff
130  port map (
131  clkIn => clkFeedBackOut,
132  clkOutP => adcClkP,
133  clkOutN => adcClkN);
134 
135  SynchronizerOneShot_0 : entity work.SynchronizerOneShot
136  generic map (
137  TPD_G => TPD_G,
138  BYPASS_SYNC_G => false)
139  port map (
140  clk => clkFeedBackOut,
141  dataIn => adcSync,
142  dataOut => sync);
143 
144  ODDR_0 : ODDR
145  generic map(
146  DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
147  INIT => '0', -- Initial value for Q port ('1' or '0')
148  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
149  port map (
150  D1 => sync, -- 1-bit data input (positive edge)
151  D2 => sync, -- 1-bit data input (negative edge)
152  Q => syncOut, -- 1-bit DDR output
153  C => clkFeedBackOut, -- 1-bit clock input
154  CE => '1', -- 1-bit clock enable input
155  R => '0', -- 1-bit reset
156  S => '0'); -- 1-bit set
157 
158  OBUFDS_0 : OBUFDS
159  port map(
160  I => syncOut,
161  O => adcSyncP,
162  OB => adcSyncN);
163 
164  adcClock <= adcClk;
165 
166  end generate;
167 
168  GEN_NO_PLL : if (USE_PLL_G = false and XIL_DEVICE_G = "7SERIES") generate
169 
170  ClkOutBufDiff_1 : entity work.ClkOutBufDiff
171  port map (
172  clkIn => adcClk,
173  rstIn => adcRst,
174  clkOutP => adcClkP,
175  clkOutN => adcClkN);
176 
177  SynchronizerOneShot_1 : entity work.SynchronizerOneShot
178  generic map (
179  TPD_G => TPD_G,
180  BYPASS_SYNC_G => true)
181  port map (
182  clk => adcClk,
183  dataIn => adcSync,
184  dataOut => sync);
185 
186  ODDR_1 : ODDR
187  generic map(
188  DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
189  INIT => '0', -- Initial value for Q port ('1' or '0')
190  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
191  port map (
192  D1 => sync, -- 1-bit data input (positive edge)
193  D2 => sync, -- 1-bit data input (negative edge)
194  Q => syncOut, -- 1-bit DDR output
195  C => adcClk, -- 1-bit clock input
196  CE => '1', -- 1-bit clock enable input
197  R => '0', -- 1-bit reset
198  S => '0'); -- 1-bit set
199 
200  OBUFDS_1 : OBUFDS
201  port map(
202  I => syncOut,
203  O => adcSyncP,
204  OB => adcSyncN);
205 
206  IBUFGDS_1 : IBUFGDS
207  port map (
208  I => adcClkFbP,
209  IB => adcClkFbN,
210  O => adcInClk);
211 
212  BUFG_1 : BUFG
213  port map (
214  I => adcInClk,
215  O => adcClock);
216 
217  end generate;
218 
219 
220  GEN_ULTRASCALE_NO_PLL : if (XIL_DEVICE_G = "ULTRASCALE") generate
221 
222  ClkOutBufDiff_1 : entity work.ClkOutBufDiff
223  generic map (
224  XIL_DEVICE_G => XIL_DEVICE_G)
225  port map (
226  clkIn => adcClk,
227  rstIn => adcRst,
228  clkOutP => adcClkP,
229  clkOutN => adcClkN);
230 
231  SynchronizerOneShot_1 : entity work.SynchronizerOneShot
232  generic map (
233  TPD_G => TPD_G,
234  BYPASS_SYNC_G => true)
235  port map (
236  clk => adcClk,
237  dataIn => adcSync,
238  dataOut => sync);
239 
240  ODDRE1_1 : ODDRE1
241  port map (
242  D1 => sync, -- 1-bit data input (positive edge)
243  D2 => sync, -- 1-bit data input (negative edge)
244  Q => syncOut, -- 1-bit DDR output
245  C => adcClk, -- 1-bit clock input
246  SR => '0');
247 
248  OBUFDS_1 : OBUFDS
249  port map(
250  I => syncOut,
251  O => adcSyncP,
252  OB => adcSyncN);
253 
254  IBUFGDS_1 : IBUFGDS
255  port map (
256  I => adcClkFbP,
257  IB => adcClkFbN,
258  O => adcInClk);
259 
260  BUFG_1 : BUFG
261  port map (
262  I => adcInClk,
263  O => adcClock);
264 
265 
266  end generate;
267 
268 end mapping;
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiAds42lb69Pll.XIL_DEVICE_G
XIL_DEVICE_Gstring := "7SERIES"
Definition: AxiAds42lb69Pll.vhd:33
AxiAds42lb69Pll.ADC_CLK_FREQ_G
ADC_CLK_FREQ_Greal := 250.0E+6
Definition: AxiAds42lb69Pll.vhd:32
SynchronizerOneShot.BYPASS_SYNC_G
BYPASS_SYNC_Gboolean := false
Definition: SynchronizerOneShot.vhd:30
AxiAds42lb69Pll.mapping.ADC_CLK_PERIOD_NS_C
real := 1.0E+9/ ADC_CLK_FREQ_G ADC_CLK_PERIOD_NS_C
Definition: AxiAds42lb69Pll.vhd:51
AxiAds42lb69Pll.USE_PLL_G
USE_PLL_Gboolean := true
Definition: AxiAds42lb69Pll.vhd:31
AxiAds42lb69Pll.TPD_G
TPD_Gtime := 1 ns
Definition: AxiAds42lb69Pll.vhd:30
AxiAds42lb69Pkg.ieee
_library_ ieeeieee
Definition: AxiAds42lb69Pkg.vhd:18
ClkOutBufDiff.rstIn
in rstInsl :=not RST_POLARITY_G
Definition: ClkOutBufDiff.vhd:34
ClkOutBufDiff.XIL_DEVICE_G
XIL_DEVICE_Gstring := "7SERIES"
Definition: ClkOutBufDiff.vhd:30