SURF  1.0
AxiAds42lb69DeserBit.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : AxiAds42lb69DeserBit.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-03-20
5 -- Last update: 2015-03-23
6 -------------------------------------------------------------------------------
7 -- Description: ADC DDR Deserializer
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_unsigned.all;
21 use ieee.std_logic_arith.all;
22 
23 use work.StdRtlPkg.all;
24 use work.AxiAds42lb69Pkg.all;
25 
26 library unisim;
27 use unisim.vcomponents.all;
28 
29 --! @see entity
30  --! @ingroup devices_Ti_ads42lb69
31 entity AxiAds42lb69DeserBit is
32  generic (
33  TPD_G : time := 1 ns;
34  DELAY_INIT_G : slv(8 downto 0) := (others => '0');
35  IODELAY_GROUP_G : string := "AXI_ADS42LB69_IODELAY_GRP";
36  XIL_DEVICE_G : string := "7SERIES");
37  port (
38  -- ADC Data (clk domain)
39  dataP : in sl;
40  dataN : in sl;
41  Q1 : out sl;
42  Q2 : out sl;
43  -- IO_Delay (delayClk domain)
44  delayClk : in sl;
45  delayRst : in sl;
46  delayInLoad : in sl;
47  delayInData : in slv(8 downto 0);
48  delayOutData : out slv(9 downto 0);
49  -- Clocks
50  clk : in sl);
51 end AxiAds42lb69DeserBit;
52 
53 architecture rtl of AxiAds42lb69DeserBit is
54 
55  signal data : sl;
56  signal dataDly : sl;
57  signal clkb : sl;
58  signal cascOut : sl;
59  signal cascRet : sl;
60  signal delayOutData1 : slv(8 downto 0);
61  signal delayOutData2 : slv(8 downto 0);
62 
63 begin
64 
65  GEN_7SERIES : if (XIL_DEVICE_G = "7SERIES") generate
66  attribute IODELAY_GROUP : string;
67  attribute IODELAY_GROUP of IDELAYE2_inst : label is IODELAY_GROUP_G;
68  begin
69 
70  IBUFDS_Inst : IBUFDS
71  port map (
72  I => dataP,
73  IB => dataN,
74  O => data);
75 
76  IDELAYE2_inst : IDELAYE2
77  generic map (
78  CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
79  DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN)
80  HIGH_PERFORMANCE_MODE => "FALSE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
81  IDELAY_TYPE => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
82  IDELAY_VALUE => conv_integer(DELAY_INIT_G(4 downto 0)), -- Input delay tap setting (0-31)
83  PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
84  REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
85  SIGNAL_PATTERN => "DATA") -- DATA, CLOCK input signal
86  port map (
87  CNTVALUEOUT => delayOutData(4 downto 0), -- 5-bit output: Counter value output
88  DATAOUT => dataDly, -- 1-bit output: Delayed data output
89  C => delayClk, -- 1-bit input: Clock input
90  CE => '0', -- 1-bit input: Active high enable increment/decrement input
91  CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input
92  CNTVALUEIN => delayInData(4 downto 0), -- 5-bit input: Counter value input
93  DATAIN => '0', -- 1-bit input: Internal delay data input
94  IDATAIN => data, -- 1-bit input: Data input from the I/O
95  INC => '0', -- 1-bit input: Increment / Decrement tap delay input
96  LD => '1', -- 1-bit input: Load IDELAY_VALUE input
97  LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input
98  REGRST => delayInLoad); -- 1-bit input: Active-high reset tap-delay input
99 
100  IDDR_Inst : IDDR
101  generic map (
102  DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE", or "SAME_EDGE_PIPELINED"
103  INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
104  INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
105  SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
106  port map (
107  D => dataDly, -- 1-bit DDR data input
108  C => clk, -- 1-bit clock input
109  CE => '1', -- 1-bit clock enable input
110  R => '0', -- 1-bit reset
111  S => '0', -- 1-bit set
112  Q1 => Q1, -- 1-bit output for positive edge of clock
113  Q2 => Q2); -- 1-bit output for negative edge of clock
114 
115  end generate;
116 
117  GEN_ULTRASCALE : if (XIL_DEVICE_G = "ULTRASCALE") generate
118 
119  -- when DELAY_FORMAT is "COUNT" the delay is not PVT calibrated
120  -- Therefore, do not use an IDELAYCTRL component
121  -- Leave the REFCLK_FREQUENCY attribute at the default value (300 MHz).
122  -- Tie the EN_VTC input pin Low
123 
124  IBUFDS_Inst : IBUFDS
125  port map (
126  I => dataP,
127  IB => dataN,
128  O => data);
129 
130  IDELAYE3_inst : IDELAYE3
131  generic map (
132  CASCADE => "MASTER", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
133  DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME)
134  DELAY_SRC => "IDATAIN", -- Delay input (DATAIN, IDATAIN)
135  DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
136  DELAY_VALUE => conv_integer(DELAY_INIT_G), -- Input delay value setting
137  IS_CLK_INVERTED => '0', -- Optional inversion for CLK
138  IS_RST_INVERTED => '0', -- Optional inversion for RST
139  REFCLK_FREQUENCY => 300.0, -- IDELAYCTRL clock input frequency in MHz (200.0-2400.0)
140  UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
141  port map (
142  CASC_IN => '0', -- 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
143  CASC_OUT => cascOut, -- 1-bit output: Cascade delay output to ODELAY input cascade
144  CASC_RETURN => cascRet, -- 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
145  DATAIN => '0', -- 1-bit input: Data input from the logic
146  IDATAIN => data, -- 1-bit input: Data input from the IOBUF
147  DATAOUT => dataDly, -- 1-bit output: Delayed data output
148  CLK => delayClk, -- 1-bit input: Clock input
149  EN_VTC => '0', -- 1-bit input: Keep delay constant over VT
150  INC => '0', -- 1-bit input: Increment / Decrement tap delay input
151  CE => '0', -- 1-bit input: Active high enable increment/decrement input
152  LOAD => delayInLoad, -- 1-bit input: Load DELAY_VALUE input
153  RST => delayRst, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE
154  CNTVALUEIN => delayInData, -- 9-bit input: Counter value input
155  CNTVALUEOUT => delayOutData1); -- 9-bit output: Counter value output
156 
157  ODELAYE3_inst : ODELAYE3
158  generic map (
159  CASCADE => "SLAVE_END", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
160  DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME)
161  DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
162  DELAY_VALUE => conv_integer(DELAY_INIT_G), -- Input delay value setting
163  IS_CLK_INVERTED => '0', -- Optional inversion for CLK
164  IS_RST_INVERTED => '0', -- Optional inversion for RST
165  REFCLK_FREQUENCY => 300.0, -- IDELAYCTRL clock input frequency in MHz (200.0-2400.0)
166  UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
167  port map (
168  CASC_IN => cascOut, -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT
169  CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade
170  CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT
171  ODATAIN => '0', -- 1-bit input: Data input
172  DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port
173  CLK => delayClk, -- 1-bit input: Clock input
174  EN_VTC => '0', -- 1-bit input: Keep delay constant over VT
175  INC => '0', -- 1-bit input: Increment / Decrement tap delay input
176  CE => '0', -- 1-bit input: Active high enable increment/decrement input
177  LOAD => delayInLoad, -- 1-bit input: Load DELAY_VALUE input
178  RST => delayRst, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE
179  CNTVALUEIN => delayInData, -- 9-bit input: Counter value input
180  CNTVALUEOUT => delayOutData2); -- 9-bit output: Counter value output
181 
182  delayOutData <= resize(delayOutData1, 10, '0') + delayOutData2;
183 
184  IDDR_Inst : IDDRE1
185  generic map (
186  DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE", or "SAME_EDGE_PIPELINED"
187  IS_C_INVERTED => '0')
188  port map (
189  D => dataDly, -- 1-bit DDR data input
190  C => clk, -- 1-bit clock input
191  CB => clkb, -- 1-bit inverted clock input
192  R => '0', -- 1-bit reset
193  Q1 => Q1, -- 1-bit output for positive edge of clock
194  Q2 => Q2); -- 1-bit output for negative edge of clock
195 
196  clkb <= not clk;
197 
198  end generate;
199 
200 end rtl;
AxiAds42lb69Pkg.data
slv( 8 downto 0) data
Definition: AxiAds42lb69Pkg.vhd:46
AxiAds42lb69DeserBit.delayOutData
out delayOutDataslv( 9 downto 0)
Definition: AxiAds42lb69DeserBit.vhd:48
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiAds42lb69DeserBit.IODELAY_GROUP_G
IODELAY_GROUP_Gstring := "AXI_ADS42LB69_IODELAY_GRP"
Definition: AxiAds42lb69DeserBit.vhd:35
AxiAds42lb69DeserBit.DELAY_INIT_G
DELAY_INIT_Gslv( 8 downto 0) :=( others => '0')
Definition: AxiAds42lb69DeserBit.vhd:34
AxiAds42lb69DeserBit.delayInData
in delayInDataslv( 8 downto 0)
Definition: AxiAds42lb69DeserBit.vhd:47
AxiAds42lb69Deser.unisim
_library_ unisimunisim
Definition: AxiAds42lb69Deser.vhd:26
AxiAds42lb69DeserBit.XIL_DEVICE_G
XIL_DEVICE_Gstring := "7SERIES"
Definition: AxiAds42lb69DeserBit.vhd:36
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29