SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAds42lb69DeserBit Entity Reference
devices » Ti » ads42lb69
+ Inheritance diagram for AxiAds42lb69DeserBit:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiAds42lb69Pkg  Package <AxiAds42lb69Pkg>
vcomponents 

Generics

TPD_G  time := 1 ns
DELAY_INIT_G  slv ( 8 downto 0 ) := ( others = > ' 0 ' )
IODELAY_GROUP_G  string := " AXI_ADS42LB69_IODELAY_GRP "
XIL_DEVICE_G  string := " 7SERIES "

Ports

dataP   in sl
dataN   in sl
Q1   out sl
Q2   out sl
delayClk   in sl
delayRst   in sl
delayInLoad   in sl
delayInData   in slv ( 8 downto 0 )
delayOutData   out slv ( 9 downto 0 )
clk   in sl

Detailed Description

See also
entity

Definition at line 31 of file AxiAds42lb69DeserBit.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiAds42lb69DeserBit.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G slv ( 8 downto 0 ) := ( others = > ' 0 ' )
Generic

Definition at line 34 of file AxiAds42lb69DeserBit.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " AXI_ADS42LB69_IODELAY_GRP "
Generic

Definition at line 35 of file AxiAds42lb69DeserBit.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 36 of file AxiAds42lb69DeserBit.vhd.

◆ dataP

dataP in sl
Port

Definition at line 39 of file AxiAds42lb69DeserBit.vhd.

◆ dataN

dataN in sl
Port

Definition at line 40 of file AxiAds42lb69DeserBit.vhd.

◆ Q1

Q1 out sl
Port

Definition at line 41 of file AxiAds42lb69DeserBit.vhd.

◆ Q2

Q2 out sl
Port

Definition at line 42 of file AxiAds42lb69DeserBit.vhd.

◆ delayClk

delayClk in sl
Port

Definition at line 44 of file AxiAds42lb69DeserBit.vhd.

◆ delayRst

delayRst in sl
Port

Definition at line 45 of file AxiAds42lb69DeserBit.vhd.

◆ delayInLoad

delayInLoad in sl
Port

Definition at line 46 of file AxiAds42lb69DeserBit.vhd.

◆ delayInData

delayInData in slv ( 8 downto 0 )
Port

Definition at line 47 of file AxiAds42lb69DeserBit.vhd.

◆ delayOutData

delayOutData out slv ( 9 downto 0 )
Port

Definition at line 48 of file AxiAds42lb69DeserBit.vhd.

◆ clk

clk in sl
Port

Definition at line 50 of file AxiAds42lb69DeserBit.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAds42lb69DeserBit.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAds42lb69DeserBit.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAds42lb69DeserBit.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAds42lb69DeserBit.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAds42lb69DeserBit.vhd.

◆ AxiAds42lb69Pkg

AxiAds42lb69Pkg
Package

Definition at line 24 of file AxiAds42lb69DeserBit.vhd.

◆ unisim

unisim
Library

Definition at line 26 of file AxiAds42lb69DeserBit.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file AxiAds42lb69DeserBit.vhd.

The documentation for this class was generated from the following file: