|
|
clk | in | std_logic |
|
rst | in | std_logic |
|
nReset | in | std_logic |
|
ena | in | std_logic |
|
clk_cnt | in | std_logic_vector ( 15 downto 0 ) |
|
cmd | in | std_logic_vector ( 3 downto 0 ) |
|
cmd_ack | out | std_logic |
|
busy | out | std_logic |
|
al | out | std_logic |
|
din | in | std_logic |
|
dout | out | std_logic |
|
filt | in | std_logic_vector ( ( filter- 1 ) * dynfilt downto 0 ) |
|
scl_i | in | std_logic |
|
scl_o | out | std_logic |
|
scl_oen | out | std_logic |
|
sda_i | in | std_logic |
|
sda_o | out | std_logic |
|
sda_oen | out | std_logic |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/i2c_master_bit_ctrl.vhd
- protocols/i2c/rtl/i2c_master_bit_ctrl.vhd