stdlib Package Reference

Package >> stdlib

Functions
std_logic_vector	decode ( v: in std_logic_vector )
std_ulogic	genmux ( s: in std_logic_vector , v: in std_logic_vector )
std_ulogic	xorv ( d: in std_logic_vector )
std_ulogic	orv ( d: in std_logic_vector )
std_ulogic	andv ( d: in std_logic_vector )
boolean	notx ( d: in std_logic_vector )
boolean	notx ( d: in std_ulogic )
std_logic_vector	"-" ( d: in std_logic_vector , i: in integer )
std_logic_vector	"-" ( i: in integer , d: in std_logic_vector )
std_logic_vector	"+" ( d: in std_logic_vector , i: in integer )
std_logic_vector	"+" ( i: in integer , d: in std_logic_vector )
std_logic_vector	"-" ( d: in std_logic_vector , i: in std_ulogic )
std_logic_vector	"+" ( d: in std_logic_vector , i: in std_ulogic )
std_logic_vector	"-" ( a: in std_logic_vector , b: in std_logic_vector )
std_logic_vector	"+" ( a: in std_logic_vector , b: in std_logic_vector )
std_logic_vector	"*" ( a: in std_logic_vector , b: in std_logic_vector )
std_logic_vector	unsigned_mul ( a: in std_logic_vector , b: in std_logic_vector )
std_logic_vector	signed_mul ( a: in std_logic_vector , b: in std_logic_vector )
std_logic_vector	mixed_mul ( a: in std_logic_vector b: in std_logic_vector sign: in std_logic )
boolean	"<" ( i: in integer , b: in std_logic_vector )
integer	conv_integer ( v: in std_logic_vector )
integer	conv_integer ( v: in std_logic )
std_logic_vector	conv_std_logic_vector ( i: in integer , w: in integer )
std_logic_vector	conv_std_logic_vector_signed ( i: in integer , w: in integer )
std_ulogic	conv_std_logic ( b: in boolean )
string	tost ( v: in std_logic_vector )
string	tost ( v: in std_logic )
string	tost ( i: in integer )
string	tost_any ( s: in std_ulogic )
string	tost_bits ( s: in std_logic_vector )
string	tost ( b: in boolean )
string	tost ( r: in real )

Procedures
	print( s: string )

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std
textio

Components
report_version

Constants
zero32	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
zero64	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
zero128	std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
one32	std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' )
one64	std_logic_vector ( 63 downto 0 ) := ( others = > ' 1 ' )
one128	std_logic_vector ( 127 downto 0 ) := ( others = > ' 1 ' )
log2	log2arr := ( 0 , 0 , 1 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , others = > 9 )
log2x	log2arr := ( 0 , 1 , 1 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , 8 , others = > 9 )

Types
log2arr	( 0 to 512 ) integer

Attributes
sync_set_reset	string
async_set_reset	string

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The documentation for this design unit was generated from the following file:

• protocols/i2c/rtl/stdlib.vhd