i2c_master_bit_ctrl.structural Architecture Reference

Architecture >> i2c_master_bit_ctrl::structural

Processes
gen_clken	( clk , nReset )
synch_scl_sda	( clk , nReset )
PROCESS_113	( clk )
gen_al	( clk , nReset )
sync_scl_sda	( clk , fSCL_chg , fSDA_chg , fiscl_oen_chg , fisda_oen_chg , nReset )
PROCESS_114	( clk )
gen_ald	( clk , nReset )
detect_sta_sto	( clk , nReset )
gen_busy	( clk , nReset )
gen_dout	( clk )
nxt_state_decoder	( clk , nReset )
gen_clken	( clk , nReset )
synch_scl_sda	( clk , nReset )
PROCESS_252	( clk )
gen_al	( clk , nReset )
sync_scl_sda	( clk , fSCL_chg , fSDA_chg , fiscl_oen_chg , fisda_oen_chg , nReset )
PROCESS_253	( clk )
gen_ald	( clk , nReset )
detect_sta_sto	( clk , nReset )
gen_busy	( clk , nReset )
gen_dout	( clk )
nxt_state_decoder	( clk , nReset )

Constants
I2C_CMD_NOP	std_logic_vector ( 3 downto 0 ) := " 0000 "
I2C_CMD_START	std_logic_vector ( 3 downto 0 ) := " 0001 "
I2C_CMD_STOP	std_logic_vector ( 3 downto 0 ) := " 0010 "
I2C_CMD_READ	std_logic_vector ( 3 downto 0 ) := " 0100 "
I2C_CMD_WRITE	std_logic_vector ( 3 downto 0 ) := " 1000 "
FR	integer := filter
DR	integer := filter+ 1

Types
states	( idle , start_a , start_b , start_c , start_d , start_e , start_f , start_g , stop_a , stop_b , stop_c , stop_d , rd_a , rd_b , rd_c , rd_d , wr_a , wr_b , wr_c , wr_d )

Signals
c_state	states
s_state	states
iscl_oen	std_logic
isda_oen	std_logic
sda_chk	std_logic
fSCL	std_logic_vector ( 1 downto 0 )
fSDA	std_logic_vector ( 1 downto 0 )
clk_en	std_logic
slave_wait	std_logic
ial	std_logic
cnt	std_logic_vector ( 15 downto 0 )
csync	std_logic
sta_condition	std_logic
sto_condition	std_logic
cmd_stop	std_logic
ibusy	std_logic
slvw_dis	std_logic
sSCL	std_logic_vector ( FR downto 0 )
sSDA	std_logic_vector ( FR downto 0 )
discl_oen	std_logic_vector ( DR downto 0 )
disda_oen	std_logic_vector ( DR downto 0 )
filtcnt	std_logic_vector ( filter- 1 downto 0 )
sSCL	std_logic_vector ( 1 downto 0 )
sSDA	std_logic_vector ( 1 downto 0 )
fiscl_oen	std_logic_vector ( 1 downto 0 )
fisda_oen	std_ulogic
fSCL_chg	std_ulogic
fSDA_chg	std_ulogic
fiscl_oen_chg	std_ulogic
fisda_oen_chg	std_ulogic
discl_oen	std_ulogic
disda_oen	std_ulogic

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/i2c_master_bit_ctrl.vhd
• protocols/i2c/rtl/i2c_master_bit_ctrl.vhd