dma_read_tb.dma_read_tb Architecture Reference

Architecture >> dma_read_tb::dma_read_tb

Processes
comb	( axiClkRst , axisMaster , dmaAck , r )
seq	( axiClk )
PROCESS_27	( r )
comb	( axiClkRst , axisMaster , dmaAck , r )
seq	( axiClk )
PROCESS_103	( r )

Constants
CLK_PERIOD_C	time := 4 ns
TPD_G	time := CLK_PERIOD_C/ 4
USE_PEND_C	boolean := true
BACKPRESSURE_C	boolean := true
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
AXI_CONFIG_C	AxiConfigType := ( ADDR_WIDTH_C = > 32 , DATA_BYTES_C = > 8 , ID_BITS_C = > 8 , LEN_BITS_C = > 4 )
REG_INIT_C	RegType := ( sof = > ' 1 ' , passed = > ' 0 ' , passedDly = > ' 0 ' , failed = > ( others = > ' 0 ' ) , failedDly = > ( others = > ' 0 ' ) , byteCnt = > ( others = > ' 0 ' ) , dmaReq = > AXI_READ_DMA_REQ_INIT_C , axisSlave = > AXI_STREAM_SLAVE_INIT_C , state = > INIT_S )

Types
StateType	( INIT_S , REQ_S , CHECK_S , HANDSHAKE_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
axiClk	sl
axiClkRst	sl
dmaAck	AxiReadDmaAckType
axisMaster	AxiStreamMasterType
axisSlave	AxiStreamSlaveType
axiReadMaster	AxiReadMasterType
axiReadSlave	AxiReadSlaveType

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_axireademulate	AxiReadEmulate <Entity AxiReadEmulate>
u_axistreamdmaread	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_clkrst	ClkRst <Entity ClkRst>
u_axireademulate	AxiReadEmulate <Entity AxiReadEmulate>
u_axistreamdmaread	AxiStreamDmaRead <Entity AxiStreamDmaRead>

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The documentation for this design unit was generated from the following files:

• axi/dma/tb/dma_read_tb.vhd
• build/SRC_VHDL/surf/dma_read_tb.vhd