ads54j60.rtl Architecture Reference

Architecture >> ads54j60::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , coreBusyIn , r , rdData , rdEn )
seq	( axiClk )

Constants
DLY_C	natural := integer ( 1 . 0E - 6 / CLK_PERIOD_G )
REG_INIT_C	RegType := ( busy = > ' 0 ' , rst = > ' 0 ' , axiRd = > ' 0 ' , wrEn = > ' 0 ' , wrData = > ( others = > ' 0 ' ) , data = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , xferType = > ( others = > ' 0 ' ) , timer = > 0 , cnt = > 0 , size = > 0 , wrArray = > ( others = > ( others = > ' 0 ' ) ) , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , INIT_S , REQ_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rdEn	sl
rdData	slv ( 23 downto 0 )

Records
RegType

Instantiations
u_spimaster	SpiMaster <Entity SpiMaster>

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads54j60/rtl/ads54j60.vhd