SpiMaster Entity Reference

Inheritance diagram for SpiMaster:

Entities
SpiMaster.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
math_real
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
NUM_CHIPS_G	positive range 1 to 8 := 4
DATA_SIZE_G	natural := 16
CPHA_G	sl := ' 0 '
CPOL_G	sl := ' 0 '
CLK_PERIOD_G	real := 8 . 0E - 9
SPI_SCLK_PERIOD_G	real := 1 . 0E - 6

Ports
clk	in	sl
sRst	in	sl
freeRunClk	in	sl := ' 0 '
chipSel	in	slv ( log2 ( NUM_CHIPS_G ) - 1 downto 0 )
wrEn	in	sl
wrData	in	slv ( DATA_SIZE_G- 1 downto 0 )
dataSize	in	slv ( log2 ( DATA_SIZE_G ) - 1 downto 0 ) := toSlv ( DATA_SIZE_G- 1 , log2 ( DATA_SIZE_G ) )
rdEn	out	sl
rdData	out	slv ( DATA_SIZE_G- 1 downto 0 )
shiftCount	out	slv ( bitSize ( DATA_SIZE_G ) - 1 downto 0 )
spiCsL	out	slv ( NUM_CHIPS_G- 1 downto 0 )
spiSclk	out	sl
spiSdi	out	sl
spiSdo	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/spi/rtl/SpiMaster.vhd