SpiMaster.rtl Architecture Reference

Architecture >> SpiMaster::rtl

Processes
comb	( chipSel , dataSize , freeRunClk , r , sRst , spiSdoRes , wrData , wrEn )
seq	( clk )

Constants
SPI_CLK_PERIOD_DIV2_CYCLES_C	integer := integer ( SPI_SCLK_PERIOD_G/ ( 2 . 0 * CLK_PERIOD_G ) )
SCLK_COUNTER_SIZE_C	integer := bitSize ( SPI_CLK_PERIOD_DIV2_CYCLES_C )
REG_INIT_C	RegType := ( state = > IDLE_S , rdEn = > ' 0 ' , rdData = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , dataCounter = > ( others = > ' 0 ' ) , sclkCounter = > ( others = > ' 0 ' ) , spiCsL = > ( others = > ' 1 ' ) , spiSclk = > ' 0 ' , spiSdi = > ' 0 ' )

Types
StateType	( IDLE_S , FREE_RUNNING_CLK_S , SHIFT_S , SAMPLE_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
spiSdoRes	sl

Records
RegType

---

The documentation for this design unit was generated from the following file:

• protocols/spi/rtl/SpiMaster.vhd