ads54j60 Entity Reference

Inheritance diagram for ads54j60:

Collaboration diagram for ads54j60:

Entities
ads54j60.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
CLK_PERIOD_G	real := ( 1 . 0 / 156 . 25E + 6 )
SPI_SCLK_PERIOD_G	real := 1 . 0E - 6

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
coreBusyIn	in	sl := ' 0 '
coreBusyOut	out	sl
coreRst	out	sl
coreSclk	out	sl
coreSDin	in	sl
coreSDout	out	sl
coreCsb	out	sl

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads54j60/rtl/ads54j60.vhd