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Constants | Functions | Instantiations | Signals
XadcSimpleCore.rtl Architecture Reference
Architecture >> XadcSimpleCore::rtl

Functions

slv   convTemp ( temp: in real )
slv   convPwr ( pwr: in real )
bit_vector   INIT_40_C
bit_vector   INIT_41_C
bit_vector   INIT_42_C
bit_vector   INIT_48_C
bit_vector   INIT_4A_C
bit_vector   INIT_4C_C
bit_vector   INIT_4E_C

Constants

INIT_49_C  bit_vector ( 15 downto 0 ) := to_bitvector ( toSlv ( SEQ_VAUX_SEL_EN_G ) )
INIT_4B_C  bit_vector ( 15 downto 0 ) := to_bitvector ( toSlv ( SEQ_VAUX_AVG_EN_G ) )
INIT_4D_C  bit_vector ( 15 downto 0 ) := to_bitvector ( toSlv ( SEQ_VAUX_BIPOLAR_G ) )
INIT_4F_C  bit_vector ( 15 downto 0 ) := to_bitvector ( toSlv ( SEQ_VAUX_ACQ_EN_G ) )
INIT_50_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convTemp ( TEMP_UPPER_G ) & " 0000 " )
INIT_51_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCINT_UPPER_G ) & " 0000 " )
INIT_52_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCAUX_UPPER_G ) & " 0000 " )
INIT_53_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convTemp ( OVERTEMP_LIMIT_G ) & ite ( OVERTEMP_AUTO_SHDN_G , " 0011 " , " 0000 " ) )
INIT_54_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convTemp ( TEMP_LOWER_G ) & " 0000 " )
INIT_55_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCINT_LOWER_G ) & " 0000 " )
INIT_56_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCAUX_LOWER_G ) & " 0000 " )
INIT_57_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convTemp ( OVERTEMP_RESET_G ) & " 0000 " )
INIT_58_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCBRAM_UPPER_G ) & " 0000 " )
INIT_59_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCPINT_UPPER_G ) & " 0000 " )
INIT_5A_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCPAUX_UPPER_G ) & " 0000 " )
INIT_5B_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCODDR_UPPER_G ) & " 0000 " )
INIT_5C_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCBRAM_LOWER_G ) & " 0000 " )
INIT_5D_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCPINT_LOWER_G ) & " 0000 " )
INIT_5E_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCPAUX_LOWER_G ) & " 0000 " )
INIT_5F_C  bit_vector ( 15 downto 0 ) := to_bitvector ( convPwr ( VCCODDR_LOWER_G ) & " 0000 " )

Signals

drpClk  sl
drpRst  sl
drpAddr  slv ( 6 downto 0 )
drpEn  sl
drpDi  slv ( 15 downto 0 )
drpDo  slv ( 15 downto 0 )
drpWe  sl
drpRdy  sl
drpUsrRst  sl

Instantiations

u_axilitetodrp_1  AxiLiteToDrp <Entity AxiLiteToDrp>
xadc_inst  xadc
The documentation for this design unit was generated from the following file: