XadcSimpleCore Entity Reference

Inheritance diagram for XadcSimpleCore:

Collaboration diagram for XadcSimpleCore:

Entities
XadcSimpleCore.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := true
SIM_DEVICE_G	string := " 7SERIES "
SIM_MONITOR_FILE_G	string := " design.txt "
SEQUENCER_MODE_G	string := " DEFAULT "
SAMPLING_MODE_G	string := " CONTINUOUS "
MUX_EN_G	boolean := false
ADCCLK_RATIO_G	integer range 2 to 255 := 7
SAMPLE_AVG_G	slv ( 1 downto 0 ) := " 11 "
COEF_AVG_EN_G	boolean := true
SING_ADC_CH_SEL_G	slv ( 4 downto 0 ) := " 00000 "
SING_ACQ_EN_G	boolean := false
SING_BIPOLAR_G	boolean := false
OVERTEMP_AUTO_SHDN_G	boolean := true
OVERTEMP_ALM_EN_G	boolean := false
OVERTEMP_LIMIT_G	real := 125 . 0
OVERTEMP_RESET_G	real := 50 . 0
TEMP_ALM_EN_G	boolean := false
TEMP_UPPER_G	real := 80 . 0
TEMP_LOWER_G	real := 70 . 0
VCCINT_ALM_EN_G	boolean := false
VCCINT_UPPER_G	real := 1 . 1
VCCINT_LOWER_G	real := 0 . 9
VCCAUX_ALM_EN_G	boolean := false
VCCAUX_UPPER_G	real := 1 . 9
VCCAUX_LOWER_G	real := 1 . 7
VCCBRAM_ALM_EN_G	boolean := false
VCCBRAM_UPPER_G	real := 1 . 1
VCCBRAM_LOWER_G	real := 0 . 9
VCCPINT_ALM_EN_G	boolean := false
VCCPINT_UPPER_G	real := 1 . 1
VCCPINT_LOWER_G	real := 0 . 9
VCCPAUX_ALM_EN_G	boolean := false
VCCPAUX_UPPER_G	real := 1 . 9
VCCPAUX_LOWER_G	real := 1 . 7
VCCODDR_ALM_EN_G	boolean := false
VCCODDR_UPPER_G	real := 1 . 9
VCCODDR_LOWER_G	real := 1 . 7
ADC_OFFSET_CORR_EN_G	boolean := true
ADC_GAIN_CORR_EN_G	boolean := true
SUPPLY_OFFSET_CORR_EN_G	boolean := true
SUPPLY_GAIN_CORR_EN_G	boolean := true
SEQ_XADC_CAL_SEL_EN_G	boolean := true
SEQ_VCCPINT_SEL_EN_G	boolean := false
SEQ_VCCPAUX_SEL_EN_G	boolean := false
SEQ_VCCODDR_SEL_EN_G	boolean := false
SEQ_TEMPERATURE_SEL_EN_G	boolean := false
SEQ_VCCINT_SEL_EN_G	boolean := false
SEQ_VCCAUX_SEL_EN_G	boolean := false
SEQ_VPVN_SEL_EN_G	boolean := false
SEQ_VREFP_SEL_EN_G	boolean := false
SEQ_VREFN_SEL_EN_G	boolean := false
SEQ_VCCBRAM_SEL_EN_G	boolean := false
SEQ_VAUX_SEL_EN_G	booleanArray ( 15 downto 0 ) := ( others = > false )
SEQ_XADC_CAL_AVG_EN_G	boolean := true
SEQ_VCCPINT_AVG_EN_G	boolean := true
SEQ_VCCPAUX_AVG_EN_G	boolean := true
SEQ_VCCODDR_AVG_EN_G	boolean := true
SEQ_TEMPERATURE_AVG_EN_G	boolean := true
SEQ_VCCINT_AVG_EN_G	boolean := true
SEQ_VCCAUX_AVG_EN_G	boolean := true
SEQ_VPVN_AVG_EN_G	boolean := true
SEQ_VREFP_AVG_EN_G	boolean := true
SEQ_VREFN_AVG_EN_G	boolean := true
SEQ_VCCBRAM_AVG_EN_G	boolean := true
SEQ_VAUX_AVG_EN_G	booleanArray ( 15 downto 0 ) := ( others = > true )
SEQ_VPVN_BIPOLAR_G	boolean := false
SEQ_VAUX_BIPOLAR_G	BooleanArray ( 15 downto 0 ) := ( others = > false )
SEQ_XADC_CAL_ACQ_EN_G	boolean := false
SEQ_VCCPINT_ACQ_EN_G	boolean := false
SEQ_VCCPAUX_ACQ_EN_G	boolean := false
SEQ_VCCODDR_ACQ_EN_G	boolean := false
SEQ_TEMPERATURE_ACQ_EN_G	boolean := false
SEQ_VCCINT_ACQ_EN_G	boolean := false
SEQ_VCCAUX_ACQ_EN_G	boolean := false
SEQ_VPVN_ACQ_EN_G	boolean := false
SEQ_VREFP_ACQ_EN_G	boolean := false
SEQ_VREFN_ACQ_EN_G	boolean := false
SEQ_VCCBRAM_ACQ_EN_G	boolean := false
SEQ_VAUX_ACQ_EN_G	BooleanArray ( 15 downto 0 ) := ( others = > false )

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
xadcClk	in	sl := ' 0 '
xadcRst	in	sl := ' 0 '
vpIn	in	sl := ' 0 '
vnIn	in	sl := ' 0 '
vAuxP	in	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
vAuxN	in	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
convSt	in	sl := ' 0 '
convStClk	in	sl := ' 0 '
alm	out	slv ( 7 downto 0 )
ot	out	sl
busy	out	sl
channel	out	slv ( 4 downto 0 )
eoc	out	sl
eos	out	sl
muxAddr	out	slv ( 4 downto 0 )

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd