UdpDebugBridge Entity Reference

Inheritance diagram for UdpDebugBridge:

Collaboration diagram for UdpDebugBridge:

Entities
UdpDebugBridge.stub	architecture
UdpDebugBridge.UdpDebugBridgeImpl	architecture

Libraries
IEEE
ieee
surf

Use Clauses
STD_LOGIC_1164
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
UdpDebugBridgePkg	Package <UdpDebugBridgePkg>

Generics
AXIS_CLK_FREQ_G	real := 156 . 25e6

Ports
axisClk	in	std_logic
axisRst	in	std_logic
\mAxisReq[tValid]\	in	std_logic
\mAxisReq[tData]\	in	std_logic_vector ( 1023 downto 0 )
\mAxisReq[tStrb]\	in	std_logic_vector ( 127 downto 0 )
\mAxisReq[tKeep]\	in	std_logic_vector ( 127 downto 0 )
\mAxisReq[tLast]\	in	std_logic
\mAxisReq[tDest]\	in	std_logic_vector ( 7 downto 0 )
\mAxisReq[tId]\	in	std_logic_vector ( 7 downto 0 )
\mAxisReq[tUser]\	in	std_logic_vector ( 1023 downto 0 )
\sAxisReq[tReady]\	out	std_logic
\mAxisTdo[tValid]\	out	std_logic
\mAxisTdo[tData]\	out	std_logic_vector ( 1023 downto 0 )
\mAxisTdo[tStrb]\	out	std_logic_vector ( 127 downto 0 )
\mAxisTdo[tKeep]\	out	std_logic_vector ( 127 downto 0 )
\mAxisTdo[tLast]\	out	std_logic
\mAxisTdo[tDest]\	out	std_logic_vector ( 7 downto 0 )
\mAxisTdo[tId]\	out	std_logic_vector ( 7 downto 0 )
\mAxisTdo[tUser]\	out	std_logic_vector ( 1023 downto 0 )
\sAxisTdo[tReady]\	in	std_logic
mAxisReq	in	AxiStreamMasterType
sAxisReq	out	AxiStreamSlaveType
mAxisTdo	out	AxiStreamMasterType
sAxisTdo	in	AxiStreamSlaveType

---

The documentation for this design unit was generated from the following files:

• xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd
• xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd
• xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd
• xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd
• xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd
• xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd