UdpDebugBridge.UdpDebugBridgeImpl Architecture Reference

Architecture >> UdpDebugBridge::UdpDebugBridgeImpl

Constants
XVC_TCLK_DIV2_C	positive := positive ( ieee.math_real.round ( AXIS_CLK_FREQ_G/ XVC_TCLK_FREQ_C/ 2 . 0 ) )

Instantiations
u_axisjtagdebugbridge	AxisJtagDebugBridge <Entity AxisJtagDebugBridge>
u_axisjtagdebugbridge	AxisJtagDebugBridge <Entity AxisJtagDebugBridge>

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The documentation for this design unit was generated from the following files:

• xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd
• xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd