TenGigEthGtyUltraScaleWrapper Entity Reference

Inheritance diagram for TenGigEthGtyUltraScaleWrapper:

Collaboration diagram for TenGigEthGtyUltraScaleWrapper:

Entities
TenGigEthGtyUltraScaleWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
TenGigEthPkg	Package <TenGigEthPkg>

Generics
TPD_G	time := 1 ns
NUM_LANE_G	natural range 1 to 4 := 1
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
QPLL_REFCLK_SEL_G	slv ( 2 downto 0 ) := " 001 "
EN_AXI_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigArray ( 3 downto 0 ) := ( others = > EMAC_AXIS_CONFIG_C )

Ports
localMac	in	Slv48Array ( NUM_LANE_G- 1 downto 0 ) := ( others = > MAC_ADDR_INIT_C )
dmaClk	in	slv ( NUM_LANE_G- 1 downto 0 )
dmaRst	in	slv ( NUM_LANE_G- 1 downto 0 )
dmaIbMasters	out	AxiStreamMasterArray ( NUM_LANE_G- 1 downto 0 )
dmaIbSlaves	in	AxiStreamSlaveArray ( NUM_LANE_G- 1 downto 0 )
dmaObMasters	in	AxiStreamMasterArray ( NUM_LANE_G- 1 downto 0 )
dmaObSlaves	out	AxiStreamSlaveArray ( NUM_LANE_G- 1 downto 0 )
axiLiteClk	in	slv ( NUM_LANE_G- 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteRst	in	slv ( NUM_LANE_G- 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteReadMasters	in	AxiLiteReadMasterArray ( NUM_LANE_G- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axiLiteReadSlaves	out	AxiLiteReadSlaveArray ( NUM_LANE_G- 1 downto 0 )
axiLiteWriteMasters	in	AxiLiteWriteMasterArray ( NUM_LANE_G- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axiLiteWriteSlaves	out	AxiLiteWriteSlaveArray ( NUM_LANE_G- 1 downto 0 )
extRst	in	sl
coreClk	out	sl
coreRst	out	sl
phyClk	out	slv ( NUM_LANE_G- 1 downto 0 )
phyRst	out	slv ( NUM_LANE_G- 1 downto 0 )
phyReady	out	slv ( NUM_LANE_G- 1 downto 0 )
gtClk	out	sl
gtTxPreCursor	in	slv ( 4 downto 0 ) := " 00000 "
gtTxPostCursor	in	slv ( 4 downto 0 ) := " 00000 "
gtTxDiffCtrl	in	slv ( 4 downto 0 ) := " 11100 "
gtRxPolarity	in	sl := ' 0 '
gtTxPolarity	in	sl := ' 0 '
gtRefClk	in	sl := ' 0 '
gtClkP	in	sl := ' 1 '
gtClkN	in	sl := ' 0 '
gtTxP	out	slv ( NUM_LANE_G- 1 downto 0 )
gtTxN	out	slv ( NUM_LANE_G- 1 downto 0 )
gtRxP	in	slv ( NUM_LANE_G- 1 downto 0 )
gtRxN	in	slv ( NUM_LANE_G- 1 downto 0 )

---

The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd