TenGigEthGtyUltraScaleWrapper.mapping Architecture Reference

Architecture >> TenGigEthGtyUltraScaleWrapper::mapping

Signals
qplllock	slv ( 1 downto 0 )
qplloutclk	slv ( 1 downto 0 )
qplloutrefclk	slv ( 1 downto 0 )
qpllRst	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qpllReset	slv ( 1 downto 0 )
coreClock	sl
coreReset	sl

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
tengigethgtyultrascaleclk_inst	TenGigEthGtyUltraScaleClk <Entity TenGigEthGtyUltraScaleClk>
tengigethgtyultrascale_inst	TenGigEthGtyUltraScale <Entity TenGigEthGtyUltraScale>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd