TenGigEthGtx7Clk.mapping Architecture Reference

Architecture >> TenGigEthGtx7Clk::mapping

Constants
QPLL_REFCLK_SEL_C	bit_vector := ite ( USE_GTREFCLK_G , " 111 " , QPLL_REFCLK_SEL_G )

Signals
refClockDiv2	sl
refClock	sl
refClk	sl
phyClock	sl
phyReset	sl
pwrUpRst	sl
qpllReset	sl

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
synchronizer_0	Synchronizer <Entity Synchronizer>
ibufds_gte2_inst	ibufds_gte2
clk156_bufg	bufg
gtx7quadpll_inst	Gtx7QuadPll <Entity Gtx7QuadPll>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd