Gtx7QuadPll Entity Reference

Inheritance diagram for Gtx7QuadPll:

Collaboration diagram for Gtx7QuadPll:

Entities
Gtx7QuadPll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_RESET_SPEEDUP_G	string := " TRUE "
SIM_VERSION_G	string := " 4.0 "
QPLL_CFG_G	bit_vector := x " 0680181 "
QPLL_REFCLK_SEL_G	bit_vector := " 001 "
QPLL_FBDIV_G	bit_vector := " 0100100000 "
QPLL_FBDIV_RATIO_G	bit := ' 1 '
QPLL_REFCLK_DIV_G	integer := 1
EN_DRP_G	boolean := true

Ports
qPllRefClk	in	sl
qPllOutClk	out	sl
qPllOutRefClk	out	sl
qPllLock	out	sl
qPllLockDetClk	in	sl
qPllRefClkLost	out	sl
qPllPowerDown	in	sl := ' 0 '
qPllReset	in	sl
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

---

The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd