Gtx7QuadPll.mapping Architecture Reference

Architecture >> Gtx7QuadPll::mapping

Signals
gtRefClk0	sl
gtRefClk1	sl
gtNorthRefClk0	sl
gtNorthRefClk1	sl
gtSouthRefClk0	sl
gtSouthRefClk1	sl
gtGRefClk	sl
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
drpAddr	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )

Instantiations
gtxe2_common_0_i	gtxe2_common
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd