SyncTrigRate.rtl Architecture Reference

Architecture >> SyncTrigRate::rtl

Processes
PROCESS_72	( locClk )
comb	( r , trigCntSync )
seq	( refClk )
PROCESS_172	( locClk )
comb	( r , trigCntSync )
seq	( refClk )

Constants
TIMEOUT_C	natural := getTimeRatio ( REF_CLK_FREQ_G , REFRESH_RATE_G ) - 1
REG_INIT_C	RegType := ( updated = > ' 0 ' , timer = > 0 , trigCntDly = > ( others = > ' 0 ' ) , rate = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
trig	sl := not ( IN_POLARITY_G )
trigLast	sl := not IN_POLARITY_G
updated	sl := ' 0 '
trigCnt	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
trigCntSync	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
rstStat	sl

Records
RegType

Instantiations
u_oneshot	SynchronizerOneShot <Entity SynchronizerOneShot>
syncin_trigcnt	SynchronizerFifo <Entity SynchronizerFifo>
u_sync	SyncMinMax <Entity SyncMinMax>
u_oneshot	SynchronizerOneShot <Entity SynchronizerOneShot>
syncin_trigcnt	SynchronizerFifo <Entity SynchronizerFifo>
u_sync	SyncMinMax <Entity SyncMinMax>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncTrigRate.vhd
• build/SRC_VHDL/surf/SyncTrigRate.vhd