SyncTrigRate Entity Reference

Inheritance diagram for SyncTrigRate:

Collaboration diagram for SyncTrigRate:

Entities
SyncTrigRate.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
ONE_SHOT_G	boolean := false
IN_POLARITY_G	sl := ' 1 '
COUNT_EDGES_G	boolean := false
REF_CLK_FREQ_G	real := 200 . 0E + 6
REFRESH_RATE_G	real := 1 . 0E + 0
CNT_WIDTH_G	positive := 32

Ports
trigIn	in	sl
trigRateUpdated	out	sl
trigRateOut	out	slv ( CNT_WIDTH_G- 1 downto 0 )
trigRateOutMax	out	slv ( CNT_WIDTH_G- 1 downto 0 )
trigRateOutMin	out	slv ( CNT_WIDTH_G- 1 downto 0 )
locClkEn	in	sl := ' 1 '
locClk	in	sl
locRst	in	sl := ' 0 '
refClk	in	sl
refRst	in	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncTrigRate.vhd
• build/SRC_VHDL/surf/SyncTrigRate.vhd