SugoiAxiLitePixelMatrixConfig Entity Reference

Entities
SugoiAxiLitePixelMatrixConfig.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COL_GRAY_CODE_G	boolean := true
COL_WIDTH_G	positive range 1 to 10 := 6
ROW_GRAY_CODE_G	boolean := true
ROW_WIDTH_G	positive range 1 to 10 := 6
DATA_WIDTH_G	positive range 1 to 11 := 9
TIMER_WIDTH_G	positive range 1 to 16 := 12

Ports
colAddr	out	slv ( COL_WIDTH_G- 1 downto 0 )
rowAddr	out	slv ( ROW_WIDTH_G- 1 downto 0 )
allCol	out	sl
allRow	out	sl
dataBus	inout	slv ( DATA_WIDTH_G- 1 downto 0 )
readWrite	out	sl
globalRstL	out	sl
cckReg	out	sl
cckPix	out	sl
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SugoiAxiLitePixelMatrixConfig.vhd
• protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd