Architecture >> SugoiAxiLitePixelMatrixConfig::rtl
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comb | ( axilReadMaster , axilRst , axilWriteMaster , dataIn , r ) |
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seq | ( axilClk , axilRst ) |
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comb | ( axilReadMaster , axilRst , axilWriteMaster , dataIn , r ) |
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seq | ( axilClk , axilRst ) |
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COL_DEC_ADDR_LOW_C | integer := 2 |
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COL_DEC_ADDR_HIGH_C | integer := ( COL_WIDTH_G+ COL_DEC_ADDR_LOW_C ) - 1 |
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ROW_DEC_ADDR_LOW_C | integer := COL_DEC_ADDR_HIGH_C+ 1 |
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ROW_DEC_ADDR_HIGH_C | integer := ( ROW_WIDTH_G+ ROW_DEC_ADDR_LOW_C ) - 1 |
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ADDR_PARTITION_C | integer := 2 + COL_WIDTH_G+ ROW_WIDTH_G |
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REG_INIT_C | RegType := ( colReg = > ( others = > ' 0 ' ) , colAddr = > ( others = > ' 0 ' ) , rowReg = > ( others = > ' 0 ' ) , rowAddr = > ( others = > ' 0 ' ) , allCol = > ' 0 ' , allRow = > ' 0 ' , dataOut = > ( others = > ' 0 ' ) , readWrite = > ' 1 ' , configTri = > ' 0 ' , globalRstL = > ' 0 ' , cckReg = > ' 0 ' , cckPix = > ' 0 ' , cnt = > 0 , timer = > ( others = > ' 0 ' ) , timerSize = > ( others = > ' 1 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S ) |
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StateType | ( IDLE_S , READ_CMD_S , WRITE_CMD_S ) |
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r | RegType := REG_INIT_C |
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rin | RegType |
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dataIn | slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' ) |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/SugoiAxiLitePixelMatrixConfig.vhd
- protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd